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Conference Paper: Modeling and verification of NCL circuits using PAT

TitleModeling and verification of NCL circuits using PAT
Authors
Ma, JMan, KLLim, EGZhang, NLei, CUGuan, SUJeong, TTSeon, JK
KeywordsCSP#
NCL circuits
Specification
Verfication
Issue Date2011
PublisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/wps/find/journaldescription.cws_home/719240/description#description
Citation
The 2011 International Conference on Advanced in Control Engineering and Information Science (CEIS 2011), Dali, China, 18-19 August 2011. In Procedia Engineering, 2011, v. 15 pt. 7, p. 3411-3415 How to Cite?
DOI: http://dx.doi.org/10.1016/j.proeng.2011.08.639
AbstractNULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification. © 2011 Published by Elsevier Ltd.
DescriptionThis journal vol. contains selected, peer reviewed papers from CEIS 2011
Persistent Identifierhttp://hdl.handle.net/10722/198899
ISBN
978-1-62748-564-7
ISSN
1877-7058
2020 SCImago Journal Rankings: 0.320
ISI Accession Number ID
WOS:000300876503085

 

DC FieldValueLanguage
dc.contributor.authorMa, J-
dc.contributor.authorMan, KL-
dc.contributor.authorLim, EG-
dc.contributor.authorZhang, N-
dc.contributor.authorLei, CU-
dc.contributor.authorGuan, SU-
dc.contributor.authorJeong, TT-
dc.contributor.authorSeon, JK-
dc.date.accessioned2014-07-17T03:52:28Z-
dc.date.available2014-07-17T03:52:28Z-
dc.date.issued2011-
dc.identifier.citationThe 2011 International Conference on Advanced in Control Engineering and Information Science (CEIS 2011), Dali, China, 18-19 August 2011. In Procedia Engineering, 2011, v. 15 pt. 7, p. 3411-3415-
dc.identifier.isbn978-1-62748-564-7-
dc.identifier.issn1877-7058-
dc.identifier.urihttp://hdl.handle.net/10722/198899-
dc.descriptionThis journal vol. contains selected, peer reviewed papers from CEIS 2011-
dc.description.abstractNULL Conventional Logic (NCL) is a Delay-Insensitive (DI) clockless paradigm and is suitable for implementing asynchronous circuits. Efficient methods of analysis are required to specify and verify such DI systems. Based on Delay Insensitive sequential Process (DISP) specification, this paper demonstrates the application of formal methods by applying Process Analysis Toolkit (PAT) to model and verify the behavior of NCL circuits. A few useful constructs are successfully modeled and verified by using PAT. The flexibility and simplicity of the coding, simulation and verification shows that PAT is effective and applicable for NCL circuit design and verification. © 2011 Published by Elsevier Ltd.-
dc.languageeng-
dc.publisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/wps/find/journaldescription.cws_home/719240/description#description-
dc.relation.ispartofProcedia Engineering-
dc.subjectCSP#-
dc.subjectNCL circuits-
dc.subjectSpecification-
dc.subjectVerfication-
dc.titleModeling and verification of NCL circuits using PAT-
dc.typeConference_Paper-
dc.identifier.emailLei, CU: culei@eee.hku.hk-
dc.description.naturelink_to_OA_fulltext-
dc.identifier.doi10.1016/j.proeng.2011.08.639-
dc.identifier.scopuseid_2-s2.0-84055200461-
dc.identifier.hkuros230681-
dc.identifier.volume15-
dc.identifier.issuept. 7-
dc.identifier.spage3411-
dc.identifier.epage3415-
dc.identifier.isiWOS:000300876503085-
dc.publisher.placeNetherlands-
dc.customcontrol.immutablesml 141021-
dc.identifier.issnl1877-7058-

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