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Article: Effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor
| Title | Effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor |
|---|---|
| Authors | |
| Issue Date | 2015 |
| Publisher | Electrochemical Society, Inc. The Journal's web site is located at http://ssl.ecsdl.org/ |
| Citation | ECS Solid State Letters, 2015, v. 4 n. 9, p. Q44-Q46 How to Cite? |
| Abstract | The effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 oC) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 oC) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm2/V.s) and largest on-off current ratio (3.52×108). © 2015 The Electrochemical Society. |
| Persistent Identifier | http://hdl.handle.net/10722/234050 |
| ISSN | 2016 Impact Factor: 1.184 |
| ISI Accession Number ID |
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Huang, XD | - |
| dc.contributor.author | Song, J | - |
| dc.contributor.author | Lai, PT | - |
| dc.date.accessioned | 2016-10-14T06:58:44Z | - |
| dc.date.available | 2016-10-14T06:58:44Z | - |
| dc.date.issued | 2015 | - |
| dc.identifier.citation | ECS Solid State Letters, 2015, v. 4 n. 9, p. Q44-Q46 | - |
| dc.identifier.issn | 2162-8742 | - |
| dc.identifier.uri | http://hdl.handle.net/10722/234050 | - |
| dc.description.abstract | The effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 oC) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 oC) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm2/V.s) and largest on-off current ratio (3.52×108). © 2015 The Electrochemical Society. | - |
| dc.language | eng | - |
| dc.publisher | Electrochemical Society, Inc. The Journal's web site is located at http://ssl.ecsdl.org/ | - |
| dc.relation.ispartof | ECS Solid State Letters | - |
| dc.rights | ECS Solid State Letters. Copyright © Electrochemical Society, Inc. | - |
| dc.title | Effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor | - |
| dc.type | Article | - |
| dc.identifier.email | Lai, PT: laip@eee.hku.hk | - |
| dc.identifier.authority | Lai, PT=rp00130 | - |
| dc.description.nature | postprint | - |
| dc.identifier.doi | 10.1149/2.0011509ssl | - |
| dc.identifier.scopus | eid_2-s2.0-84937540098 | - |
| dc.identifier.hkuros | 267798 | - |
| dc.identifier.volume | 4 | - |
| dc.identifier.issue | 9 | - |
| dc.identifier.spage | Q44 | - |
| dc.identifier.epage | Q46 | - |
| dc.identifier.isi | WOS:000358058400005 | - |
| dc.publisher.place | United States | - |
| dc.customcontrol.immutable | sml 161108 | - |
| dc.identifier.issnl | 2162-8750 | - |