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Article: A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

TitleA 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric
Authors
KeywordsGeOI/GeON MOSFETs
Threshold voltage
Ultra-thin-body
High-k gate dielectric
Issue Date2016
PublisherElsevier. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2016, v. 57, p. 24-33 How to Cite?
AbstractA 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.
Persistent Identifierhttp://hdl.handle.net/10722/278173
ISSN
2019 Impact Factor: 1.535
2015 SCImago Journal Rankings: 0.675

 

DC FieldValueLanguage
dc.contributor.authorJI, F-
dc.contributor.authorXU, JP-
dc.contributor.authorLIU, L-
dc.contributor.authorTANG, WM-
dc.contributor.authorLai, PT-
dc.date.accessioned2019-10-04T08:08:52Z-
dc.date.available2019-10-04T08:08:52Z-
dc.date.issued2016-
dc.identifier.citationMicroelectronics Reliability, 2016, v. 57, p. 24-33-
dc.identifier.issn0026-2714-
dc.identifier.urihttp://hdl.handle.net/10722/278173-
dc.description.abstractA 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.-
dc.languageeng-
dc.publisherElsevier. The Journal's web site is located at http://www.elsevier.com/locate/microrel-
dc.relation.ispartofMicroelectronics Reliability-
dc.subjectGeOI/GeON MOSFETs-
dc.subjectThreshold voltage-
dc.subjectUltra-thin-body-
dc.subjectHigh-k gate dielectric-
dc.titleA 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric-
dc.typeArticle-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1016/j.microrel.2015.12.004-
dc.identifier.scopuseid_2-s2.0-84958927756-
dc.identifier.hkuros306915-
dc.identifier.volume57-
dc.identifier.spage24-
dc.identifier.epage33-
dc.publisher.placeUnited Kingdom-

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