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Conference Paper: A New Optimization Cost Model for VLSI Standard Cell Placement

TitleA New Optimization Cost Model for VLSI Standard Cell Placement
Authors
Cheung, PYSYeung, CSKTse, SKYuen, CKKo, WL
KeywordsElectronics
Issue Date1997
PublisherIEEE.
Citation
The 1997 IEEE International Symposium on Circuits and Systems Hong Kong, China, 9-12 June 1997. In IEEE International Symposium on Circuits and Systems Proceedings, 1997, v. 3, p. 1708-1711 How to Cite?
DOI: http://dx.doi.org/10.1109/ISCAS.1997.621464
AbstractIn this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.
Persistent Identifierhttp://hdl.handle.net/10722/46014
ISSN
0271-4302
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorCheung, PYSen_HK
dc.contributor.authorYeung, CSKen_HK
dc.contributor.authorTse, SKen_HK
dc.contributor.authorYuen, CKen_HK
dc.contributor.authorKo, WLen_HK
dc.date.accessioned2007-10-30T06:40:39Z-
dc.date.available2007-10-30T06:40:39Z-
dc.date.issued1997en_HK
dc.identifier.citationThe 1997 IEEE International Symposium on Circuits and Systems Hong Kong, China, 9-12 June 1997. In IEEE International Symposium on Circuits and Systems Proceedings, 1997, v. 3, p. 1708-1711en_HK
dc.identifier.issn0271-4302en_HK
dc.identifier.urihttp://hdl.handle.net/10722/46014-
dc.description.abstractIn this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.en_HK
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofHistoric Title IEEE International Symposium on Circuits and Systems Proceedings-
dc.rights©1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectElectronicsen_HK
dc.titleA New Optimization Cost Model for VLSI Standard Cell Placementen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0271-4302&volume=3&spage=1708&epage=1711&date=1997&atitle=A+New+Optimization+Cost+Model+for+VLSI+Standard+Cell+Placementen_HK
dc.identifier.emailCheung, PYS:paul.cheung@hku.hk-
dc.identifier.authorityCheung, PYS=rp00077-
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/ISCAS.1997.621464en_HK
dc.identifier.scopuseid_2-s2.0-0030673643-
dc.identifier.hkuros27304-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0030673643&selection=ref&src=s&origin=recordpage-
dc.identifier.volume3-
dc.identifier.spage1708-
dc.identifier.epage1711-
dc.identifier.scopusauthoridCheung, PYS=7202595335-
dc.identifier.scopusauthoridYeung, CSK=7201354219-
dc.identifier.scopusauthoridTse, SK=36239675600-
dc.identifier.scopusauthoridYuen, CK=7101633438-
dc.identifier.scopusauthoridKo, WL=7202286803-
dc.customcontrol.immutablesml 151028 - merged-
dc.identifier.issnl0271-4302-

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