On the design of an SoPC based multi-core embedded system

Abstract

Due to the advancements of VLSI technologies, we can put more cores on a chip, resulting in the emergence of multi-core embedded systems. This also brings great challenges to traditional parallel processing as to how we can increase the performance of applications with increased number of cores. In this paper, we meet the challenges using a novel approach. Specifically, we propose an SoPC (System-on-Programmable-Chip) based multi-core embedded system. Under our proposed system, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of applications. We have built a prototype of the system using FPGAs. Experimental evaluation demonstrates significant system efficiency of the proposed system in terms of computation and power consumption. © 2008 IEEE.