Hybrid reconfigurable architecture for low power digital signal processing system

Abstract

This paper presents an architecture for a hybrid re-configurable device which is specifically optimized for acoustic applications. In the proposed architecture, Finegrained units are used for implementing control logic and bit-oriented operations, while parameterised and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and fast fourier transformation (FFT) are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block (WEB) scheme is proposed to model embedded blocks using existing FPGA tools. This methodology involves adopting existing FPGA resources to model the size, position and delay of the embedded elements. We show significant power reduction when comparing with existing reconfigurable device implementing the same acoustic applications. © 2010 IEEE.