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- Publisher Website: 10.1109/LED.2020.3026931
- Scopus: eid_2-s2.0-85094871912
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Article: High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory
Title | High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory |
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Authors | |
Keywords | nonvolatile contralateral-gated neural networks transition metal dichalcogenide (TMD) MoS 2 Charge-trap memory |
Issue Date | 2020 |
Citation | IEEE Electron Device Letters, 2020, v. 41, n. 11, p. 1649-1652 How to Cite? |
Abstract | The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained. |
Persistent Identifier | http://hdl.handle.net/10722/297988 |
ISSN | 2023 Impact Factor: 4.1 2023 SCImago Journal Rankings: 1.250 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Chung, Yun Yan | - |
dc.contributor.author | Cheng, Chao Ching | - |
dc.contributor.author | Chou, Yu Che | - |
dc.contributor.author | Chueh, Wei Chen | - |
dc.contributor.author | Chung, Wan Hsuan | - |
dc.contributor.author | Yu, Zhihao | - |
dc.contributor.author | Hung, Terry Yi Tse | - |
dc.contributor.author | Huang, Lin Yun | - |
dc.contributor.author | Wang, Shin Yuan | - |
dc.contributor.author | Teng, Li Cheng | - |
dc.contributor.author | Chang, Wen Ho | - |
dc.contributor.author | Li, Lain Jong | - |
dc.contributor.author | Chien, Chao Hsin | - |
dc.date.accessioned | 2021-04-08T03:07:25Z | - |
dc.date.available | 2021-04-08T03:07:25Z | - |
dc.date.issued | 2020 | - |
dc.identifier.citation | IEEE Electron Device Letters, 2020, v. 41, n. 11, p. 1649-1652 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10722/297988 | - |
dc.description.abstract | The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained. | - |
dc.language | eng | - |
dc.relation.ispartof | IEEE Electron Device Letters | - |
dc.subject | nonvolatile | - |
dc.subject | contralateral-gated | - |
dc.subject | neural networks | - |
dc.subject | transition metal dichalcogenide (TMD) | - |
dc.subject | MoS 2 | - |
dc.subject | Charge-trap memory | - |
dc.title | High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory | - |
dc.type | Article | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/LED.2020.3026931 | - |
dc.identifier.scopus | eid_2-s2.0-85094871912 | - |
dc.identifier.volume | 41 | - |
dc.identifier.issue | 11 | - |
dc.identifier.spage | 1649 | - |
dc.identifier.epage | 1652 | - |
dc.identifier.eissn | 1558-0563 | - |
dc.identifier.isi | WOS:000584248800009 | - |
dc.identifier.issnl | 0741-3106 | - |