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- Publisher Website: 10.1109/IEDM13553.2020.9372072
- Scopus: eid_2-s2.0-85102919144
- WOS: WOS:000717011600181
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Conference Paper: Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET
Title | Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET |
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Authors | |
Issue Date | 2020 |
Publisher | IEEE. |
Citation | 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 12-18 December 2020. In International Electron Devices Meeting (IEDM), 2020 How to Cite? |
Abstract | We propose a novel triple-gated single transistor comprising monolayer MoS 2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS 2 n-FET and switchable easily through top-gate bias setting (V LOW / V HIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS 2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications. |
Persistent Identifier | http://hdl.handle.net/10722/299186 |
ISSN | 2023 SCImago Journal Rankings: 1.047 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Chung, YY | - |
dc.contributor.author | Cheng, CC | - |
dc.contributor.author | Kang, BK | - |
dc.contributor.author | Chueh, WC | - |
dc.contributor.author | Wang, SY | - |
dc.contributor.author | Chou, CH | - |
dc.contributor.author | Hung, TYT | - |
dc.contributor.author | Wang, SY | - |
dc.contributor.author | Chang, WH | - |
dc.contributor.author | Li, LJ | - |
dc.contributor.author | Chien, CH | - |
dc.date.accessioned | 2021-04-30T07:25:22Z | - |
dc.date.available | 2021-04-30T07:25:22Z | - |
dc.date.issued | 2020 | - |
dc.identifier.citation | 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 12-18 December 2020. In International Electron Devices Meeting (IEDM), 2020 | - |
dc.identifier.issn | 0163-1918 | - |
dc.identifier.uri | http://hdl.handle.net/10722/299186 | - |
dc.description.abstract | We propose a novel triple-gated single transistor comprising monolayer MoS 2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS 2 n-FET and switchable easily through top-gate bias setting (V LOW / V HIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS 2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications. | - |
dc.language | eng | - |
dc.publisher | IEEE. | - |
dc.relation.ispartof | International Electron Devices Meeting (IEDM) | - |
dc.title | Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET | - |
dc.type | Conference_Paper | - |
dc.identifier.email | Li, LJ: lanceli1@hku.hk | - |
dc.identifier.authority | Li, LJ=rp02799 | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/IEDM13553.2020.9372072 | - |
dc.identifier.scopus | eid_2-s2.0-85102919144 | - |
dc.identifier.hkuros | 700003941 | - |
dc.identifier.isi | WOS:000717011600181 | - |