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Article: High-κ perovskite membranes as insulators for two-dimensional transistors

TitleHigh-κ perovskite membranes as insulators for two-dimensional transistors
Authors
Issue Date2022
Citation
Nature, 2022, v. 605 n. 7909, p. 262-267 How to Cite?
AbstractThe scaling of silicon metal–oxide–semiconductor field-effect transistors has followed Moore’s law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10−2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems.
Persistent Identifierhttp://hdl.handle.net/10722/315481
ISSN
2023 Impact Factor: 50.5
2023 SCImago Journal Rankings: 18.509
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorHuang, J-
dc.contributor.authorWan, Y-
dc.contributor.authorShi, J-
dc.contributor.authorZhang, J-
dc.contributor.authorWang, Z-
dc.contributor.authorWang, W-
dc.contributor.authorYang, N-
dc.contributor.authorLiu, Y-
dc.contributor.authorLin, C-
dc.contributor.authorGuan, X-
dc.contributor.authorHu, L-
dc.contributor.authorYang, Z-
dc.contributor.authorHuang, B-
dc.contributor.authorChiu, Y-
dc.contributor.authorYang, J-
dc.contributor.authorTung, V-
dc.contributor.authorWang, D-
dc.contributor.authorZadeh, K-
dc.contributor.authorWu, T-
dc.contributor.authorZu, X-
dc.contributor.authorQiao, L-
dc.contributor.authorLi, L-
dc.contributor.authorLi, S-
dc.date.accessioned2022-08-19T08:58:42Z-
dc.date.available2022-08-19T08:58:42Z-
dc.date.issued2022-
dc.identifier.citationNature, 2022, v. 605 n. 7909, p. 262-267-
dc.identifier.issn0028-0836-
dc.identifier.urihttp://hdl.handle.net/10722/315481-
dc.description.abstractThe scaling of silicon metal–oxide–semiconductor field-effect transistors has followed Moore’s law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10−2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems.-
dc.languageeng-
dc.relation.ispartofNature-
dc.titleHigh-κ perovskite membranes as insulators for two-dimensional transistors-
dc.typeArticle-
dc.identifier.emailWan, Y: wanyi@hku.hk-
dc.identifier.emailLi, L: lanceli1@hku.hk-
dc.identifier.authorityLi, L=rp02799-
dc.identifier.doi10.1038/s41586-022-04588-2-
dc.identifier.pmid35546188-
dc.identifier.scopuseid_2-s2.0-85130633806-
dc.identifier.hkuros335492-
dc.identifier.volume605-
dc.identifier.issue7909-
dc.identifier.spage262-
dc.identifier.epage267-
dc.identifier.isiWOS:000794004500018-

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