Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Abstract

Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-kappa gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO3 thin dielectrics with a monolayer CVD MoS2, where the optimized SrTiO3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5x10(-2) A/cm(2)). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to similar to 75 mV dec(-1) and a large ON/OFF current ratio of 10(6).