File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: An efficient algorithm for RLC buffer insertion

TitleAn efficient algorithm for RLC buffer insertion
Authors
Issue Date2007
Citation
Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, 2007, p. 171-175 How to Cite?
AbstractTraditional buffer insertion algorithms neglect the impact of inductance effect, which often introduces large error in circuit optimization. On the other hand, ultra-fast buffering techniques are always desirable as buffering is such a widely used technique in industry. It is a challenge to design an RLC buffering algorithm which excels in both runtime and solution quality. In this paper, such an algorithm is proposed. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. Experiment results on industrial netlists demonstrate that the new algorithm consistently outperforms van Ginneken/Lillis algorithm [1], [2] for RC buffering and all known RLC buffering algorithms. Without buffer cost minimization, the new algorithm saves up to 8.5% buffer area and provides up to 4× speedup over Ismail's algorithm [3]. When buffer cost minimization is handled, the new algorithm uses 33.4% fewer buffers than van Ginnenken-Lillis's algorithm, and saves up to 5.3% buffer area and gives up to 5x speedup compared to the algorithm in [4]. © 2007 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/336055

 

DC FieldValueLanguage
dc.contributor.authorJiang, Zhanyuan-
dc.contributor.authorHu, Shiyan-
dc.contributor.authorHu, Jiang-
dc.contributor.authorShi, Weiping-
dc.date.accessioned2024-01-15T08:22:24Z-
dc.date.available2024-01-15T08:22:24Z-
dc.date.issued2007-
dc.identifier.citationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, 2007, p. 171-175-
dc.identifier.urihttp://hdl.handle.net/10722/336055-
dc.description.abstractTraditional buffer insertion algorithms neglect the impact of inductance effect, which often introduces large error in circuit optimization. On the other hand, ultra-fast buffering techniques are always desirable as buffering is such a widely used technique in industry. It is a challenge to design an RLC buffering algorithm which excels in both runtime and solution quality. In this paper, such an algorithm is proposed. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. Experiment results on industrial netlists demonstrate that the new algorithm consistently outperforms van Ginneken/Lillis algorithm [1], [2] for RC buffering and all known RLC buffering algorithms. Without buffer cost minimization, the new algorithm saves up to 8.5% buffer area and provides up to 4× speedup over Ismail's algorithm [3]. When buffer cost minimization is handled, the new algorithm uses 33.4% fewer buffers than van Ginnenken-Lillis's algorithm, and saves up to 5.3% buffer area and gives up to 5x speedup compared to the algorithm in [4]. © 2007 IEEE.-
dc.languageeng-
dc.relation.ispartofProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007-
dc.titleAn efficient algorithm for RLC buffer insertion-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ISQED.2007.33-
dc.identifier.scopuseid_2-s2.0-34548128231-
dc.identifier.spage171-
dc.identifier.epage175-

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats