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Article: Utilizing redundancy for timing critical interconnect

TitleUtilizing redundancy for timing critical interconnect
Authors
KeywordsNon-tree
Redundancy
Routing
Steiner network
Variation
Issue Date2007
Citation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007, v. 15, n. 10, p. 1067-1080 How to Cite?
AbstractConventionally, the topology of signal net routing is almost always restricted to Steiner trees, either unbuffered or buffered. However, introducing redundant paths into the topology (which leads to non-tree) may significantly improve timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nanoscale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable. We propose Steiner network construction heuristics which can generate either tree or non-tree with different slack-wirelength tradeoff, and handle both long path and short path constraints. We also propose heuristics for simultaneous Steiner network construction and buffering, which may provide further improvement in slack and resistance to variations. Furthermore, incremental non-tree delay update techniques are developed to facilitate fast Steiner network evaluations. Extensive experiments in different scenarios show that our heuristics usually improve timing slack by hundreds of pico seconds compared to traditional approaches. When process variations are considered, our heuristics can significantly improve timing yield because of nominal slack improvement and delay variability reduction. © 2007 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/336056
ISSN
2023 Impact Factor: 2.8
2023 SCImago Journal Rankings: 0.937
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorHu, Shiyan-
dc.contributor.authorLi, Qiuyang-
dc.contributor.authorHu, Jiang-
dc.contributor.authorLi, Peng-
dc.date.accessioned2024-01-15T08:22:25Z-
dc.date.available2024-01-15T08:22:25Z-
dc.date.issued2007-
dc.identifier.citationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007, v. 15, n. 10, p. 1067-1080-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://hdl.handle.net/10722/336056-
dc.description.abstractConventionally, the topology of signal net routing is almost always restricted to Steiner trees, either unbuffered or buffered. However, introducing redundant paths into the topology (which leads to non-tree) may significantly improve timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nanoscale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable. We propose Steiner network construction heuristics which can generate either tree or non-tree with different slack-wirelength tradeoff, and handle both long path and short path constraints. We also propose heuristics for simultaneous Steiner network construction and buffering, which may provide further improvement in slack and resistance to variations. Furthermore, incremental non-tree delay update techniques are developed to facilitate fast Steiner network evaluations. Extensive experiments in different scenarios show that our heuristics usually improve timing slack by hundreds of pico seconds compared to traditional approaches. When process variations are considered, our heuristics can significantly improve timing yield because of nominal slack improvement and delay variability reduction. © 2007 IEEE.-
dc.languageeng-
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systems-
dc.subjectNon-tree-
dc.subjectRedundancy-
dc.subjectRouting-
dc.subjectSteiner network-
dc.subjectVariation-
dc.titleUtilizing redundancy for timing critical interconnect-
dc.typeArticle-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/TVLSI.2007.903911-
dc.identifier.scopuseid_2-s2.0-34648860561-
dc.identifier.volume15-
dc.identifier.issue10-
dc.identifier.spage1067-
dc.identifier.epage1080-
dc.identifier.isiWOS:000249740800002-

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