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Conference Paper: Variation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit

TitleVariation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit
Authors
KeywordsCarbon-nanotube field effect transistor (CNFET) circuit
Statistical static timing analysis (SSTA)
Statistical timing optimization
Timing-yield improvement
Variation-aware placement
Issue Date2018
Citation
ACM Transactions on Design Automation of Electronic Systems, 2018, v. 23, n. 4, article no. A44 How to Cite?
AbstractAs the conventional silicon-based CMOS technology marches toward the sub-10nm region, the problem of high power density becomes increasingly serious. Under this circumstance, the carbon-nanotube field effect transistors (CNFETs) emerge as a promising alternative to the conventional silicon-based CMOS devices. However, they experience a much larger variation than the silicon-based CMOS devices, which results in a large circuit delay variation and hence, a significant timing yield loss. One of the main variation sources is the carbon-nanotube (CNT) density variation. However, it shows a special property not existing for silicon-based CMOS devices, namely the asymmetric spatial correlation. In this work, we propose novel global placement algorithms to reduce the timing yield loss caused by the CNT density variation. To effectively reduce the statistical circuit delay, we first develop a statistical delay measure for a segment of gates. Based on this measure, we further develop a segment-based strategy and a path-based placement strategy to reduce the delays of the statistically critical paths. Experimental results demonstrated that both of our approaches effectively improve the timing yield.
Persistent Identifierhttp://hdl.handle.net/10722/336202
ISSN
2023 Impact Factor: 2.2
2023 SCImago Journal Rankings: 0.569
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorWang, Chen-
dc.contributor.authorSun, Yanan-
dc.contributor.authorHu, Shiyan-
dc.contributor.authorJiang, Li-
dc.contributor.authorQian, Weikang-
dc.date.accessioned2024-01-15T08:24:25Z-
dc.date.available2024-01-15T08:24:25Z-
dc.date.issued2018-
dc.identifier.citationACM Transactions on Design Automation of Electronic Systems, 2018, v. 23, n. 4, article no. A44-
dc.identifier.issn1084-4309-
dc.identifier.urihttp://hdl.handle.net/10722/336202-
dc.description.abstractAs the conventional silicon-based CMOS technology marches toward the sub-10nm region, the problem of high power density becomes increasingly serious. Under this circumstance, the carbon-nanotube field effect transistors (CNFETs) emerge as a promising alternative to the conventional silicon-based CMOS devices. However, they experience a much larger variation than the silicon-based CMOS devices, which results in a large circuit delay variation and hence, a significant timing yield loss. One of the main variation sources is the carbon-nanotube (CNT) density variation. However, it shows a special property not existing for silicon-based CMOS devices, namely the asymmetric spatial correlation. In this work, we propose novel global placement algorithms to reduce the timing yield loss caused by the CNT density variation. To effectively reduce the statistical circuit delay, we first develop a statistical delay measure for a segment of gates. Based on this measure, we further develop a segment-based strategy and a path-based placement strategy to reduce the delays of the statistically critical paths. Experimental results demonstrated that both of our approaches effectively improve the timing yield.-
dc.languageeng-
dc.relation.ispartofACM Transactions on Design Automation of Electronic Systems-
dc.subjectCarbon-nanotube field effect transistor (CNFET) circuit-
dc.subjectStatistical static timing analysis (SSTA)-
dc.subjectStatistical timing optimization-
dc.subjectTiming-yield improvement-
dc.subjectVariation-aware placement-
dc.titleVariation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1145/3175500-
dc.identifier.scopuseid_2-s2.0-85053395135-
dc.identifier.volume23-
dc.identifier.issue4-
dc.identifier.spagearticle no. A44-
dc.identifier.epagearticle no. A44-
dc.identifier.eissn1557-7309-
dc.identifier.isiWOS:000455950300004-

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