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Article: FPGA adders: performance evaluation and optimal design

TitleFPGA adders: performance evaluation and optimal design
Authors
Xing, SYu, WWH
Issue Date1998
PublisherIEEE. The Journal's web site is located at http://www.computer.org/dt
Citation
IEEE Design & Test of Computers, 1998, v. 15 n. 1, p. 24-29 How to Cite?
DOI: http://dx.doi.org/10.1109/54.655179
AbstractDelay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.
Persistent Identifierhttp://hdl.handle.net/10722/42983
ISSN
0740-7475
2012 Impact Factor: 1.623
ISI Accession Number ID
WOS:000072123900012

 

DC FieldValueLanguage
dc.contributor.authorXing, Sen_HK
dc.contributor.authorYu, WWHen_HK
dc.date.accessioned2007-03-23T04:36:04Z-
dc.date.available2007-03-23T04:36:04Z-
dc.date.issued1998en_HK
dc.identifier.citationIEEE Design & Test of Computers, 1998, v. 15 n. 1, p. 24-29en_HK
dc.identifier.issn0740-7475en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42983-
dc.description.abstractDelay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.en_HK
dc.format.extent107651 bytes-
dc.format.extent25088 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.languageengen_HK
dc.publisherIEEE. The Journal's web site is located at http://www.computer.org/dten_HK
dc.relation.ispartofIEEE Design & Test of Computers-
dc.rights©1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.titleFPGA adders: performance evaluation and optimal designen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0740-7475&volume=15&issue=1&spage=24&epage=29&date=1998&atitle=FPGA+adders:+performance+evaluation+and+optimal+designen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/54.655179en_HK
dc.identifier.scopuseid_2-s2.0-0031677758-
dc.identifier.hkuros37798-
dc.identifier.isiWOS:000072123900012-
dc.identifier.issnl0740-7475-

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