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Article: Si ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides

TitleSi ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides
Authors
KeywordsAnnealing
flatband voltage
low energy ion beam
silicon nanocrystal (nc-Si)
Issue Date2006
PublisherIEEE.
Citation
IEEE Transactions on Electron Devices, 2006, v. 53 n. 5, p. 1280-1282 How to Cite?
AbstractEffect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.
Persistent Identifierhttp://hdl.handle.net/10722/45281
ISSN
2023 Impact Factor: 2.9
2023 SCImago Journal Rankings: 0.785
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorNg, CYen_HK
dc.contributor.authorChen, TPen_HK
dc.contributor.authorDing, Len_HK
dc.contributor.authorChen, Qen_HK
dc.contributor.authorLiu, Yen_HK
dc.contributor.authorZhao, Pen_HK
dc.contributor.authorTseng, AAen_HK
dc.contributor.authorFung, SHYen_HK
dc.date.accessioned2007-10-30T06:21:39Z-
dc.date.available2007-10-30T06:21:39Z-
dc.date.issued2006en_HK
dc.identifier.citationIEEE Transactions on Electron Devices, 2006, v. 53 n. 5, p. 1280-1282en_HK
dc.identifier.issn0018-9383en_HK
dc.identifier.urihttp://hdl.handle.net/10722/45281-
dc.description.abstractEffect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.en_HK
dc.format.extent121365 bytes-
dc.format.extent13983 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/pdf-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofIEEE Transactions on Electron Devices-
dc.rights©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectAnnealingen_HK
dc.subjectflatband voltageen_HK
dc.subjectlow energy ion beamen_HK
dc.subjectsilicon nanocrystal (nc-Si)en_HK
dc.titleSi ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxidesen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0018-9383&volume=53&issue=5&spage=1280&epage=1282&date=2006&atitle=Si+ion-induced+instability+in+flatband+Voltage+of+Si/sup++/-implanted+gate+oxidesen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/TED.2006.871841en_HK
dc.identifier.scopuseid_2-s2.0-33646021031-
dc.identifier.hkuros115545-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-33646021031&selection=ref&src=s&origin=recordpage-
dc.identifier.isiWOS:000237369800043-
dc.identifier.scopusauthoridNg, CY=8604409400-
dc.identifier.scopusauthoridChen, TP=7405540443-
dc.identifier.scopusauthoridDing, L=21233704100-
dc.identifier.scopusauthoridChen, Q=55209752700-
dc.identifier.scopusauthoridLiu, Y=36064444100-
dc.identifier.scopusauthoridZhao, P=8521897200-
dc.identifier.scopusauthoridTseng, AA=7102916705-
dc.identifier.scopusauthoridFung, S=7201970040-
dc.identifier.issnl0018-9383-

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