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Conference Paper: Balanced truncation for time-delay systems via approximate gramians

TitleBalanced truncation for time-delay systems via approximate gramians
Authors
Wang, XWang, QZhang, ZChen, QWong, N
KeywordsBalanced truncation
Computational costs
Delay elements
Frequency domains
Gramians
Issue Date2011
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000194
Citation
The 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, Japan, 25-28 January 2011. In Proceedings of the 16th ASP-DAC, 2011, p. 55-60, paper 1C-2 How to Cite?
DOI: http://dx.doi.org/10.1109/ASPDAC.2011.5722251
AbstractIn circuit simulation, when a large RLC network is connected with delay elements, such as transmission lines, the resulting system is a time-delay system (TDS). This paper presents a new model order reduction (MOR) scheme for TDSs with state time delays. It is the first time to reduce a TDS using balanced truncation. The Lyapunov-type equations for TDSs are derived, and an analysis of their computational complexity is presented. To reduce the computational cost, we approximate the controllability and observability Gramians in the frequency domain. The reduced-order models (ROMs) are then obtained by balancing and truncating the approximate Gramians. Numerical examples are presented to verify the accuracy and efficiency of the proposed algorithm. ©2011 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/140205
ISBN
978-1-4244-7516-2
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorWang, Xen_HK
dc.contributor.authorWang, Qen_HK
dc.contributor.authorZhang, Zen_HK
dc.contributor.authorChen, Qen_HK
dc.contributor.authorWong, Nen_HK
dc.date.accessioned2011-09-23T06:08:47Z-
dc.date.available2011-09-23T06:08:47Z-
dc.date.issued2011en_HK
dc.identifier.citationThe 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, Japan, 25-28 January 2011. In Proceedings of the 16th ASP-DAC, 2011, p. 55-60, paper 1C-2en_HK
dc.identifier.isbn978-1-4244-7516-2-
dc.identifier.urihttp://hdl.handle.net/10722/140205-
dc.description.abstractIn circuit simulation, when a large RLC network is connected with delay elements, such as transmission lines, the resulting system is a time-delay system (TDS). This paper presents a new model order reduction (MOR) scheme for TDSs with state time delays. It is the first time to reduce a TDS using balanced truncation. The Lyapunov-type equations for TDSs are derived, and an analysis of their computational complexity is presented. To reduce the computational cost, we approximate the controllability and observability Gramians in the frequency domain. The reduced-order models (ROMs) are then obtained by balancing and truncating the approximate Gramians. Numerical examples are presented to verify the accuracy and efficiency of the proposed algorithm. ©2011 IEEE.en_HK
dc.languageengen_US
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000194-
dc.relation.ispartofAsia and South Pacific Design Automation Conference Proceedingsen_HK
dc.subjectBalanced truncation-
dc.subjectComputational costs-
dc.subjectDelay elements-
dc.subjectFrequency domains-
dc.subjectGramians-
dc.titleBalanced truncation for time-delay systems via approximate gramiansen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailWang, X: xwang@eee.hku.hken_HK
dc.identifier.emailWang, Q: wangqing@hku.hken_HK
dc.identifier.emailZhang, Z: zzhang@eee.hku.hk-
dc.identifier.emailChen, Q: quanchen@eee.hku.hk-
dc.identifier.emailWong, N: nwong@eee.hku.hk-
dc.identifier.authorityWong, N=rp00190en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ASPDAC.2011.5722251en_HK
dc.identifier.scopuseid_2-s2.0-79952925430en_HK
dc.identifier.hkuros192304en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-79952925430&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage55en_HK
dc.identifier.epage60en_HK
dc.publisher.placeUnited States-
dc.description.otherThe 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, Japan, 25-28 January 2011. In Proceedings of the 16th ASP-DAC, 2011, p. 55-60, paper 1C-2-
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridChen, Q=18133382800en_HK
dc.identifier.scopusauthoridZhang, Z=35390468200en_HK
dc.identifier.scopusauthoridWang, Q=9335766700en_HK
dc.identifier.scopusauthoridWang, X=37049503000en_HK

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