File Download
There are no files associated with this item.
Links for fulltext
(May Require Subscription)
- Publisher Website: 10.1016/j.proeng.2011.08.638
- Scopus: eid_2-s2.0-84055178560
- WOS: WOS:000300876503084
- Find via
Supplementary
- Citations:
- Appears in Collections:
Conference Paper: Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips
Title | Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips |
---|---|
Authors | |
Keywords | Network-on-Chips Fault tolerant Routing |
Issue Date | 2011 |
Citation | Procedia Engineering, 2011, v. 15, p. 3406-3410 How to Cite? |
Abstract | We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example. © 2011 Published by Elsevier Ltd. |
Persistent Identifier | http://hdl.handle.net/10722/198898 |
ISSN | 2020 SCImago Journal Rankings: 0.320 |
ISI Accession Number ID |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Man, K. L. | - |
dc.contributor.author | Yedluri, Karthik | - |
dc.contributor.author | Kapoor, Hemangee K. | - |
dc.contributor.author | Lei, Chi-Un | - |
dc.contributor.author | Lim, Enggee | - |
dc.contributor.author | Ma, Jieming | - |
dc.date.accessioned | 2014-07-17T03:52:28Z | - |
dc.date.available | 2014-07-17T03:52:28Z | - |
dc.date.issued | 2011 | - |
dc.identifier.citation | Procedia Engineering, 2011, v. 15, p. 3406-3410 | - |
dc.identifier.issn | 1877-7058 | - |
dc.identifier.uri | http://hdl.handle.net/10722/198898 | - |
dc.description.abstract | We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent faults. The proposed approach is adaptive and distributed, and does not require extra circuitry or routing tables for fault tolerance operation. Deadlock handling and multiple hop links checking are included for a robust system operation. We demonstrate the algorithm mechanism using a mesh example. © 2011 Published by Elsevier Ltd. | - |
dc.language | eng | - |
dc.relation.ispartof | Procedia Engineering | - |
dc.subject | Network-on-Chips | - |
dc.subject | Fault tolerant | - |
dc.subject | Routing | - |
dc.title | Highly resilient minimal path routing algorithm for fault tolerant Network-on-Chips | - |
dc.type | Conference_Paper | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1016/j.proeng.2011.08.638 | - |
dc.identifier.scopus | eid_2-s2.0-84055178560 | - |
dc.identifier.hkuros | 230682 | - |
dc.identifier.volume | 15 | - |
dc.identifier.spage | 3406 | - |
dc.identifier.epage | 3410 | - |
dc.identifier.isi | WOS:000300876503084 | - |
dc.identifier.issnl | 1877-7058 | - |