Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Abstract

Statistical variability in ultra-scaled CMOS devices is a major challenge faced by the semiconductor industry today. It has critical impact on functionality and yield, particularly of static random access memory (SRAM) circuits. This chapter focuses on the physical origins of statistical variability and their manifestation in fully depleted (FD) thin-body silicon-on-insulator (TB-SOI) transistors. We first review the major sources of statistical variability in CMOS devices. Then, the unique impact of statistical variability on TB-SOI technology is presented, drawing comparisons with conventional, bulk metal oxide semiconductor field effect transistor (MOSFET). Finally, based on a comparison study between TB-SOI and double gate technologies, the statistical aspects of reliability are discussed.