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- Publisher Website: 10.1007/s11227-015-1415-y
- Scopus: eid_2-s2.0-84938083559
- WOS: WOS:000357345600018
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Article: Latency-aware DVFS for Efficient Power State Transitions on Many-core Architectures
Title | Latency-aware DVFS for Efficient Power State Transitions on Many-core Architectures |
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Authors | |
Keywords | Dynamic voltage and frequency scaling Many-core processors Power management Profiling Shared virtual memory The single-chip cloud computer |
Issue Date | 2015 |
Publisher | Kluwer Academic. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0920-8542 |
Citation | Journal of Supercomputing, 2015, v. 71, p. 2720-2747 How to Cite? |
Abstract | Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy---delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects. |
Persistent Identifier | http://hdl.handle.net/10722/217760 |
ISSN | 2023 Impact Factor: 2.5 2023 SCImago Journal Rankings: 0.763 |
ISI Accession Number ID |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lai, Z | - |
dc.contributor.author | Lam, KT | - |
dc.contributor.author | Wang, CL | - |
dc.contributor.author | Su, J | - |
dc.date.accessioned | 2015-09-18T06:12:25Z | - |
dc.date.available | 2015-09-18T06:12:25Z | - |
dc.date.issued | 2015 | - |
dc.identifier.citation | Journal of Supercomputing, 2015, v. 71, p. 2720-2747 | - |
dc.identifier.issn | 0920-8542 | - |
dc.identifier.uri | http://hdl.handle.net/10722/217760 | - |
dc.description.abstract | Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy---delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects. | - |
dc.language | eng | - |
dc.publisher | Kluwer Academic. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0920-8542 | - |
dc.relation.ispartof | Journal of Supercomputing | - |
dc.subject | Dynamic voltage and frequency scaling | - |
dc.subject | Many-core processors | - |
dc.subject | Power management | - |
dc.subject | Profiling | - |
dc.subject | Shared virtual memory | - |
dc.subject | The single-chip cloud computer | - |
dc.title | Latency-aware DVFS for Efficient Power State Transitions on Many-core Architectures | - |
dc.type | Article | - |
dc.identifier.email | Lam, KT: kingtin@HKUCC-COM.hku.hk | - |
dc.identifier.email | Wang, CL: clwang@cs.hku.hk | - |
dc.identifier.authority | Wang, CL=rp00183 | - |
dc.identifier.doi | 10.1007/s11227-015-1415-y | - |
dc.identifier.scopus | eid_2-s2.0-84938083559 | - |
dc.identifier.hkuros | 251504 | - |
dc.identifier.volume | 71 | - |
dc.identifier.spage | 2720 | - |
dc.identifier.epage | 2747 | - |
dc.identifier.eissn | 1573-0484 | - |
dc.identifier.isi | WOS:000357345600018 | - |
dc.publisher.place | MA, USA | - |
dc.identifier.issnl | 0920-8542 | - |