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Article: Fundamental Limit to Scaling Si Field-Effect Transistors Due to Source-to-Drain Direct Tunneling

TitleFundamental Limit to Scaling Si Field-Effect Transistors Due to Source-to-Drain Direct Tunneling
Authors
KeywordsAtomistic simulation
Density functional tight binding
Metal–oxide–semiconductor field-effect transistor (MOSFET)
Quantum transport
Issue Date2019
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16
Citation
IEEE Transactions on Electron Devices, 2019, v. 66 n. 3, p. 1167-1173 How to Cite?
AbstractHow far can the miniaturization of metal–oxide–semiconductor field-effect transistors (MOSFETs) continue is a recurring question, essential to all aspects of digital technology. Recent claims of well-performing MOSFETs with gate lengths below 4 nm apparently defy the fundamental limit of source-to-drain direct tunneling (SDDT). Here, we investigate that limit by simulating gate-all-around Si nanowire FETs with gate lengths between 8 and 3 nm using the state-of-the-art atomistic quantum transport modeling. We find that at 3-nm gate length, the current is dominated by SDDT, resulting in large source–drain leakage and poor switching performance even if the gate modulates the potential barrier between the source and drain sufficiently well. However, at 6-nm gate-length SDDT barely starts to degrade the subthreshold characteristics at large drain bias, and the ballistic ON-/OFF-current ratio is ∼10 6 with a subthreshold swing of 70 mV/decade, on par with contemporary Si technology. This means that in the best case, the technology roadmap could potentially be extended for several generations beyond the currently projected nodes. In addition, the results substantiate that the experimental devices with the claimed gate lengths below 6 nm in fact operate with a longer effective gate lengths. © 2019 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/279299
ISSN
2019 Impact Factor: 2.913
2015 SCImago Journal Rankings: 1.436
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorMarkov, SN-
dc.contributor.authorKwok, YH-
dc.contributor.authorLi, J-
dc.contributor.authorZhou, W-
dc.contributor.authorZhou, Y-
dc.contributor.authorChen, G-
dc.date.accessioned2019-10-25T13:53:02Z-
dc.date.available2019-10-25T13:53:02Z-
dc.date.issued2019-
dc.identifier.citationIEEE Transactions on Electron Devices, 2019, v. 66 n. 3, p. 1167-1173-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10722/279299-
dc.description.abstractHow far can the miniaturization of metal–oxide–semiconductor field-effect transistors (MOSFETs) continue is a recurring question, essential to all aspects of digital technology. Recent claims of well-performing MOSFETs with gate lengths below 4 nm apparently defy the fundamental limit of source-to-drain direct tunneling (SDDT). Here, we investigate that limit by simulating gate-all-around Si nanowire FETs with gate lengths between 8 and 3 nm using the state-of-the-art atomistic quantum transport modeling. We find that at 3-nm gate length, the current is dominated by SDDT, resulting in large source–drain leakage and poor switching performance even if the gate modulates the potential barrier between the source and drain sufficiently well. However, at 6-nm gate-length SDDT barely starts to degrade the subthreshold characteristics at large drain bias, and the ballistic ON-/OFF-current ratio is ∼10 6 with a subthreshold swing of 70 mV/decade, on par with contemporary Si technology. This means that in the best case, the technology roadmap could potentially be extended for several generations beyond the currently projected nodes. In addition, the results substantiate that the experimental devices with the claimed gate lengths below 6 nm in fact operate with a longer effective gate lengths. © 2019 IEEE.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16-
dc.relation.ispartofIEEE Transactions on Electron Devices-
dc.rightsIEEE Transactions on Electron Devices. Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectAtomistic simulation-
dc.subjectDensity functional tight binding-
dc.subjectMetal–oxide–semiconductor field-effect transistor (MOSFET)-
dc.subjectQuantum transport-
dc.titleFundamental Limit to Scaling Si Field-Effect Transistors Due to Source-to-Drain Direct Tunneling-
dc.typeArticle-
dc.identifier.emailKwok, YH: balloonr@hku.hk-
dc.identifier.emailLi, J: lijunhku@hku.hk-
dc.identifier.emailChen, G: ghchen@hku.hk-
dc.identifier.authorityMarkov, SN=rp02107-
dc.identifier.authorityChen, G=rp00671-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/TED.2019.2894967-
dc.identifier.scopuseid_2-s2.0-85062302245-
dc.identifier.hkuros308215-
dc.identifier.volume66-
dc.identifier.issue3-
dc.identifier.spage1167-
dc.identifier.epage1173-
dc.identifier.isiWOS:000460970400005-
dc.publisher.placeUnited States-

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