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Conference Paper: A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks

TitleA Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks
Authors
KeywordsDeep residual network
in-memory computing
CMOS-ReRAM accelerator
trained quantization
Issue Date2019
PublisherIEEE. The Journal's web site is located at https://ieeexplore.ieee.org/xpl/conhome/1000054/all-proceedings
Citation
The 13th International Conference on ASIC (ASICON 2019), Chongqing, China, 29 October-1 November 2019 How to Cite?
AbstractWe present an in-memory accelerator circuit design for ResNet-50, a large-scale residual neural network with 49 convolutional layers, 2.6 × 10 7 parameters and 4.1 × 10 9 floating-point operations (FLOPS). A 4-bit quantized ResNet-50 is first chosen among various bitwidths for the best trade-off. It is then trained and fully mapped onto a 4608 × 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top-5 accuracy on ImageNet, only 2.5% lower than the full-precision original. Two versatile CMOS 4-bit DAC and ADC are designed for input and readout, allowing the proposed CMOS-ReRAM accelerator to achieve up to 15.2× runtime speedup and 498× higher energy efficiency versus the state-of-the-art CMOS-ASIC implementation.
Persistent Identifierhttp://hdl.handle.net/10722/289866
ISSN

 

DC FieldValueLanguage
dc.contributor.authorCheng, Y-
dc.contributor.authorWong, N-
dc.contributor.authorLiu, X-
dc.contributor.authorNi, L-
dc.contributor.authorChen, HB-
dc.contributor.authorYu, H-
dc.date.accessioned2020-10-22T08:18:36Z-
dc.date.available2020-10-22T08:18:36Z-
dc.date.issued2019-
dc.identifier.citationThe 13th International Conference on ASIC (ASICON 2019), Chongqing, China, 29 October-1 November 2019-
dc.identifier.issn2162-7541-
dc.identifier.urihttp://hdl.handle.net/10722/289866-
dc.description.abstractWe present an in-memory accelerator circuit design for ResNet-50, a large-scale residual neural network with 49 convolutional layers, 2.6 × 10 7 parameters and 4.1 × 10 9 floating-point operations (FLOPS). A 4-bit quantized ResNet-50 is first chosen among various bitwidths for the best trade-off. It is then trained and fully mapped onto a 4608 × 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top-5 accuracy on ImageNet, only 2.5% lower than the full-precision original. Two versatile CMOS 4-bit DAC and ADC are designed for input and readout, allowing the proposed CMOS-ReRAM accelerator to achieve up to 15.2× runtime speedup and 498× higher energy efficiency versus the state-of-the-art CMOS-ASIC implementation.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at https://ieeexplore.ieee.org/xpl/conhome/1000054/all-proceedings-
dc.relation.ispartofInternational Conference on ASIC (ASICON)-
dc.rightsInternational Conference on ASIC (ASICON). Copyright © IEEE.-
dc.rights©2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectDeep residual network-
dc.subjectin-memory computing-
dc.subjectCMOS-ReRAM accelerator-
dc.subjecttrained quantization-
dc.titleA Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks-
dc.typeConference_Paper-
dc.identifier.emailCheng, Y: cyuan328@hku.hk-
dc.identifier.emailWong, N: nwong@eee.hku.hk-
dc.identifier.authorityWong, N=rp00190-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ASICON47005.2019.8983497-
dc.identifier.scopuseid_2-s2.0-85082595551-
dc.identifier.hkuros315884-
dc.publisher.placeUnited States-

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