An Efficient & Programmable FPGA-Based Approach for Fast-Tuning Silicon CPU Design for Embedded Systems

Abstract

Given the increasing complexity of modern Application-specific Integrated Circuits (ASIC), design verification becomes a tedious process for digital system engineers [1]. In view of this, an efficient and reliable verification scheme would benefit the IC development community. In this paper, a programmer (We can also call it as a debugger) including UART (universal asynchronous receiver/transmitter), protocol parser finite state machine (FSM), and memory interface is introduced. It offers a holistic infrastructure for programming and debugging silicon CPU designs of embedded systems in order to facilitate IC performance validation. The design of this programmer and its integration to an 8051 micro-controller unit (MCU) is presented. We also provide Hardware Description Language (HDL) simulation results to prove our system feasibility.