Si ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides

Abstract

Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.