File Download
Supplementary
-
Citations:
- Appears in Collections:
Conference Paper: Tri-Level Bit-Stream Signal Processing Circuits and Applications
| Title | Tri-Level Bit-Stream Signal Processing Circuits and Applications |
|---|---|
| Authors | |
| Issue Date | 2007 |
| Citation | The 1st International Conference on Signal Processing and Communication Systems, Gold Coast, Australia, 17-19 December 2007 How to Cite? |
| Abstract | We present signal processing building blocks for trilevel
bit-stream signal processing (BSSP). These architectures
are the 2-bit extensions from the existing 1-bit BSSP circuit
modules. It is shown that the 2-bit designs offer better
performance than their 1-bit counterparts. FPGA
implementation results of both 1-bit and 2-bit designs are
compared in terms of their hardware complexity. Finally, a
digital phase locked loop (DPLL) and a quadrature phase-shift
keying (QPSK) demodulator are presented as application
examples of the proposed circuits. |
| Persistent Identifier | http://hdl.handle.net/10722/99689 |
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Ng, CW | en_HK |
| dc.contributor.author | Wong, N | en_HK |
| dc.contributor.author | Ng, TS | en_HK |
| dc.date.accessioned | 2010-09-25T18:40:24Z | - |
| dc.date.available | 2010-09-25T18:40:24Z | - |
| dc.date.issued | 2007 | en_HK |
| dc.identifier.citation | The 1st International Conference on Signal Processing and Communication Systems, Gold Coast, Australia, 17-19 December 2007 | - |
| dc.identifier.uri | http://hdl.handle.net/10722/99689 | - |
| dc.description.abstract | We present signal processing building blocks for trilevel bit-stream signal processing (BSSP). These architectures are the 2-bit extensions from the existing 1-bit BSSP circuit modules. It is shown that the 2-bit designs offer better performance than their 1-bit counterparts. FPGA implementation results of both 1-bit and 2-bit designs are compared in terms of their hardware complexity. Finally, a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator are presented as application examples of the proposed circuits. | - |
| dc.language | eng | en_HK |
| dc.relation.ispartof | International Conference on Signal Processing and Communication Systems | en_HK |
| dc.rights | ©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
| dc.title | Tri-Level Bit-Stream Signal Processing Circuits and Applications | en_HK |
| dc.type | Conference_Paper | en_HK |
| dc.identifier.email | Wong, N: nwong@eee.hku.hk | en_HK |
| dc.identifier.email | Ng, TS: tsng@eee.hku.hk | en_HK |
| dc.identifier.authority | Wong, N=rp00190 | en_HK |
| dc.identifier.authority | Ng, TS=rp00159 | en_HK |
| dc.description.nature | published_or_final_version | - |
| dc.identifier.hkuros | 152279 | en_HK |