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Article: On IIR-based bit-stream multipliers

TitleOn IIR-based bit-stream multipliers
Authors
Ng, CWWong, NSo, HKHNg, TS
KeywordsFPGA
IIR-filters
multiplier circuits
sigma-delta modulation
Issue Date2011
PublisherJohn Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976
Citation
International Journal Of Circuit Theory And Applications, 2011, v. 39 n. 2, p. 149-158 How to Cite?
DOI: http://dx.doi.org/10.1002/cta.623
AbstractWe analyze the existing bi-level IIR-based bit-stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi-level design to tri- and quad-level architectures that offer better signal-to-noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR-based bit-stream multipliers. Useful design guidelines are subsequently drawn. © 2010 John Wiley & Sons, Ltd.
Persistent Identifierhttp://hdl.handle.net/10722/129212
ISSN
0098-9886
2022 Impact Factor: 2.3
2020 SCImago Journal Rankings: 0.364
ISI Accession Number ID
WOS:000287160200005
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorNg, CWen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorSo, HKHen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2010-12-23T08:33:39Z-
dc.date.available2010-12-23T08:33:39Z-
dc.date.issued2011en_HK
dc.identifier.citationInternational Journal Of Circuit Theory And Applications, 2011, v. 39 n. 2, p. 149-158en_HK
dc.identifier.issn0098-9886en_HK
dc.identifier.urihttp://hdl.handle.net/10722/129212-
dc.description.abstractWe analyze the existing bi-level IIR-based bit-stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi-level design to tri- and quad-level architectures that offer better signal-to-noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR-based bit-stream multipliers. Useful design guidelines are subsequently drawn. © 2010 John Wiley & Sons, Ltd.en_HK
dc.languageengen_US
dc.publisherJohn Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976en_HK
dc.relation.ispartofInternational Journal of Circuit Theory and Applicationsen_HK
dc.rightsInternational Journal of Circuit Theory and Applications. Copyright © John Wiley & Sons Ltd.-
dc.subjectFPGAen_HK
dc.subjectIIR-filtersen_HK
dc.subjectmultiplier circuitsen_HK
dc.subjectsigma-delta modulationen_HK
dc.titleOn IIR-based bit-stream multipliersen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0098-9886&volume=39&issue=2&spage=149&epage=158&date=2011&atitle=On+IIR-based+bit-stream+multipliers-
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailSo, HKH:hso@eee.hku.hken_HK
dc.identifier.emailNg, TS:tsng@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authoritySo, HKH=rp00169en_HK
dc.identifier.authorityNg, TS=rp00159en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1002/cta.623en_HK
dc.identifier.scopuseid_2-s2.0-79951598017en_HK
dc.identifier.hkuros177997en_US
dc.identifier.hkuros192282-
dc.identifier.hkuros196954-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-79951598017&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume39en_HK
dc.identifier.issue2en_HK
dc.identifier.spage149en_HK
dc.identifier.epage158en_HK
dc.identifier.isiWOS:000287160200005-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridNg, CW=36747471300en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridSo, HKH=10738896800en_HK
dc.identifier.scopusauthoridNg, TS=7402229975en_HK
dc.identifier.issnl0098-9886-

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