RECURSIVE ADDITION AND ITS PARAMETERIZATION IN VLSI.

Abstract

This paper describes the specification, simulation and implementation of a parallel addition algorithm based on the recursive methodology. The features of this recursive addition algorithm are regularity, modularity, local interconnections, intensive pipelining and concurrency which are advantageous in real-time signal processing. The recursivity of the approach to be described allows high-level addition structures to be parameterized and built into a silicon compilation environment which may facilitate design automation in VLSI signal processing. The algorithm has been proven by a mixed-mode simulation which shows a favorable 155. 5 ns worst case bandwidth at 1. 56 w power dissipation for a 32-bit 5 mu m NMOS version. Comparison of the recursive algorithm with carry lookahead addition (CLA), carry propagate addition (CPA), Brent/Kung CLA, conditional sum addition and carry select addition is in favor of the recursive addition at word sizes smaller or equal to 16.