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Article: A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric

TitleA fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric
Authors
Ji, FXu, JPLai, PTGuan, JG
Issue Date2008
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2008, v. 48 n. 5, p. 693-697 How to Cite?
DOI: http://dx.doi.org/10.1016/j.microrel.2008.01.007
AbstractAn analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated. © 2008 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/155463
ISSN
0026-2714
2023 Impact Factor: 1.6
2023 SCImago Journal Rankings: 0.394
ISI Accession Number ID
WOS:000256611400004
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorJi, Fen_US
dc.contributor.authorXu, JPen_US
dc.contributor.authorLai, PTen_US
dc.contributor.authorGuan, JGen_US
dc.date.accessioned2012-08-08T08:33:38Z-
dc.date.available2012-08-08T08:33:38Z-
dc.date.issued2008en_US
dc.identifier.citationMicroelectronics Reliability, 2008, v. 48 n. 5, p. 693-697en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://hdl.handle.net/10722/155463-
dc.description.abstractAn analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated. © 2008 Elsevier Ltd. All rights reserved.en_US
dc.languageengen_US
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrelen_US
dc.relation.ispartofMicroelectronics Reliabilityen_US
dc.titleA fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectricen_US
dc.typeArticleen_US
dc.identifier.emailLai, PT:laip@eee.hku.hken_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.microrel.2008.01.007en_US
dc.identifier.scopuseid_2-s2.0-43049156556en_US
dc.identifier.hkuros150348-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-43049156556&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume48en_US
dc.identifier.issue5en_US
dc.identifier.spage693en_US
dc.identifier.epage697en_US
dc.identifier.isiWOS:000256611400004-
dc.publisher.placeUnited Kingdomen_US
dc.identifier.scopusauthoridJi, F=8238553900en_US
dc.identifier.scopusauthoridXu, JP=7407003499en_US
dc.identifier.scopusauthoridLai, PT=7202946460en_US
dc.identifier.scopusauthoridGuan, JG=7201449685en_US
dc.identifier.issnl0026-2714-

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