Influence of natridation annealing of HfTiO on electrical properties of MOS device

Abstract

HfTiO gate dielectric is first deposited on Si wafer through co-sputtering method. The influences of post-deposition annealing (PDA) in NO, N 2O, NH 3 and N 2 ambients on the electrical properties of MOS device are studied. It is found that NO-annealed sample exhibits good electrical properties, i.e. low interface-state density, low gate leakage current and high reliability due to formation of a SiO 2/Si-like interface of HfTiSiON interlayer. In addition, based on the relationship between the physical thickness change (ΔT ox) of gate dielectric (HfTiON/HfTi-SiON), the capacitance equivalent thickness changes (ΔCET) of MOS and the k value of HfTiON dielectric, the dielectric constant of HfTiON with PDA in NO ambient is found to be 28.