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- Publisher Website: 10.1016/j.microrel.2012.04.006
- Scopus: eid_2-s2.0-84867571811
- WOS: WOS:000310767400003
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Article: Performance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layer
Title | Performance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layer |
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Authors | |
Issue Date | 2012 |
Publisher | Pergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel |
Citation | Microelectronics Reliability, 2012, v. 52 n. 11, p. 2527-2531 How to Cite? |
Abstract | The charge-trapping properties of band-engineered SrTiO 3/HfON stack were investigated by using the Al/Al 2O 3/SrTiO 3-HfON/SiO 2/Si structure. By adding the HfON layer, the undesirable silicate interlayer due to the reaction of SrTiO 3 with SiO 2 was suppressed as confirmed by X-ray photoelectron spectroscopy, transmission electron microscopy and secondary ion mass spectroscopy. Large memory window (10.6 V at ±12-V sweeping voltage) and high program speed (3.2 V at +12 V for 100 μs) are obtained for this proposed device. Moreover, it exhibits better retention property than another device without the HfON layer (charge loss of 20.0% versus 48.8%) due to suppressed charge-leakage path resulting from the good HfON/SiO 2 interface and band-engineered charge-trapping structure consisting of SrTiO 3 and HfON. © 2012 Elsevier Ltd. All rights reserved. |
Persistent Identifier | http://hdl.handle.net/10722/155757 |
ISSN | 2023 Impact Factor: 1.6 2023 SCImago Journal Rankings: 0.394 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Huang, XD | en_US |
dc.contributor.author | Lai, PT | en_US |
dc.contributor.author | Sin, JKO | en_US |
dc.date.accessioned | 2012-08-08T08:35:12Z | - |
dc.date.available | 2012-08-08T08:35:12Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.citation | Microelectronics Reliability, 2012, v. 52 n. 11, p. 2527-2531 | en_US |
dc.identifier.issn | 0026-2714 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/155757 | - |
dc.description.abstract | The charge-trapping properties of band-engineered SrTiO 3/HfON stack were investigated by using the Al/Al 2O 3/SrTiO 3-HfON/SiO 2/Si structure. By adding the HfON layer, the undesirable silicate interlayer due to the reaction of SrTiO 3 with SiO 2 was suppressed as confirmed by X-ray photoelectron spectroscopy, transmission electron microscopy and secondary ion mass spectroscopy. Large memory window (10.6 V at ±12-V sweeping voltage) and high program speed (3.2 V at +12 V for 100 μs) are obtained for this proposed device. Moreover, it exhibits better retention property than another device without the HfON layer (charge loss of 20.0% versus 48.8%) due to suppressed charge-leakage path resulting from the good HfON/SiO 2 interface and band-engineered charge-trapping structure consisting of SrTiO 3 and HfON. © 2012 Elsevier Ltd. All rights reserved. | en_US |
dc.language | eng | en_US |
dc.publisher | Pergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel | en_US |
dc.relation.ispartof | Microelectronics Reliability | en_US |
dc.title | Performance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layer | en_US |
dc.type | Article | en_US |
dc.identifier.email | Lai, PT:laip@eee.hku.hk | en_US |
dc.identifier.authority | Lai, PT=rp00130 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.doi | 10.1016/j.microrel.2012.04.006 | en_US |
dc.identifier.scopus | eid_2-s2.0-84867571811 | en_US |
dc.identifier.hkuros | 225947 | - |
dc.identifier.isi | WOS:000310767400003 | - |
dc.publisher.place | United Kingdom | en_US |
dc.identifier.scopusauthorid | Huang, XD=55217786600 | en_US |
dc.identifier.scopusauthorid | Lai, PT=7202946460 | en_US |
dc.identifier.scopusauthorid | Sin, JKO=7103312667 | en_US |
dc.identifier.citeulike | 11815066 | - |
dc.identifier.issnl | 0026-2714 | - |