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Conference Paper: SECOND GENERATION SILICON COMPILER FOR BIT-SERIAL SIGNAL PROCESSING ARCHITECTURE.

TitleSECOND GENERATION SILICON COMPILER FOR BIT-SERIAL SIGNAL PROCESSING ARCHITECTURE.
Authors
Cheung, YSLeung, SC
Issue Date1987
Citation
Icassp, Ieee International Conference On Acoustics, Speech And Signal Processing - Proceedings, 1987, p. 487-490 How to Cite?
AbstractA silicon compiler for bit-serial signal-processing architecture is described. Some of its features are inherited from the FIRST compiler. A description language is designed to provide a higher-level abstraction and concise specification of physical systems. The compiler automatically computes all the necessary timing requirements for bit-serial time-alignment and generates the necessary control networks. Two examples, a second order autorecursive filter and a fast Fourier transform processor are used as illustrations of the features provided by the compiler.
Persistent Identifierhttp://hdl.handle.net/10722/158016
ISSN
0736-7791
2023 SCImago Journal Rankings: 1.050

 

DC FieldValueLanguage
dc.contributor.authorCheung, YSen_US
dc.contributor.authorLeung, SCen_US
dc.date.accessioned2012-08-08T08:57:43Z-
dc.date.available2012-08-08T08:57:43Z-
dc.date.issued1987en_US
dc.identifier.citationIcassp, Ieee International Conference On Acoustics, Speech And Signal Processing - Proceedings, 1987, p. 487-490en_US
dc.identifier.issn0736-7791en_US
dc.identifier.urihttp://hdl.handle.net/10722/158016-
dc.description.abstractA silicon compiler for bit-serial signal-processing architecture is described. Some of its features are inherited from the FIRST compiler. A description language is designed to provide a higher-level abstraction and concise specification of physical systems. The compiler automatically computes all the necessary timing requirements for bit-serial time-alignment and generates the necessary control networks. Two examples, a second order autorecursive filter and a fast Fourier transform processor are used as illustrations of the features provided by the compiler.en_US
dc.languageengen_US
dc.relation.ispartofICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedingsen_US
dc.titleSECOND GENERATION SILICON COMPILER FOR BIT-SERIAL SIGNAL PROCESSING ARCHITECTURE.en_US
dc.typeConference_Paperen_US
dc.identifier.emailCheung, YS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, YS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0023168993en_US
dc.identifier.spage487en_US
dc.identifier.epage490en_US
dc.identifier.scopusauthoridCheung, YS=7202595335en_US
dc.identifier.scopusauthoridLeung, SC=36894171200en_US
dc.identifier.issnl0736-7791-

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