Effective BIST scheme for delay testing

Abstract

This paper presents a BIST scheme for the detection of path delay faults. It differs from the traditional BIST schemes which aim at stuck-at faults by offering higher capability of two-pattern generation. The TPG scheme produces test sequences having exactly the same robust path delay fault coverage as single-input-change test sequences. By determining nonadjacent inputs, the reduction of both test length and area overhead can be achieved. Signature analysis under path delay fault is also discussed. Based on true-value simulation, error patterns under path delay fault model were obtained and were used in aliasing estimation.