Exploiting BIST approach for two-pattern testing

Abstract

Detection of delay and transistor stuck-open faults requires two-pattern tests. BIST provides a low-cost test solution. This paper exploits BIST approach for two-pattern testing. The generation of pseudo-deterministic test-pair sequence with LFSR was exploited. A three-step approach is proposed. First, a set of deterministic test-pair is generated to detect all robust path delay faults. Second, LFSR-based TPG configurations is calculated to have pre-generated test-pair embedded in a set of maximal length pseudo-random test sequences. Third, a global cost-optimal BIST solution for data path (using pseudo-deterministic TPGs) is proposed. The second step is formulated as a cluster-covering problem. The third step is formulated as an 0-1 ILP. Experimental results are presented to demonstrate the effectiveness of the proposed approach.