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Conference Paper: Threshold voltage model of SiGe channel pMOSFET without Si cap layer

TitleThreshold voltage model of SiGe channel pMOSFET without Si cap layer
Authors
Zou, XLi, CXXu, JPLai, PTChen, WB
Issue Date2006
Citation
2005 Ieee Conference On Electron Devices And Solid-State Circuits, Edssc, 2006, p. 123-126 How to Cite?
DOI: http://dx.doi.org/10.1109/EDSSC.2005.1635221
AbstractAn analytical model on the threshold voltage of SiGe-channel pMOSFET without Si cap layer is developed by solving the Poisson's equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data and results from BSIM4, and good agreements are confirmed. © 2005 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/158514
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorZou, Xen_US
dc.contributor.authorLi, CXen_US
dc.contributor.authorXu, JPen_US
dc.contributor.authorLai, PTen_US
dc.contributor.authorChen, WBen_US
dc.date.accessioned2012-08-08T09:00:01Z-
dc.date.available2012-08-08T09:00:01Z-
dc.date.issued2006en_US
dc.identifier.citation2005 Ieee Conference On Electron Devices And Solid-State Circuits, Edssc, 2006, p. 123-126en_US
dc.identifier.urihttp://hdl.handle.net/10722/158514-
dc.description.abstractAn analytical model on the threshold voltage of SiGe-channel pMOSFET without Si cap layer is developed by solving the Poisson's equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data and results from BSIM4, and good agreements are confirmed. © 2005 IEEE.en_US
dc.languageengen_US
dc.relation.ispartof2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSCen_US
dc.titleThreshold voltage model of SiGe channel pMOSFET without Si cap layeren_US
dc.typeConference_Paperen_US
dc.identifier.emailLai, PT:laip@eee.hku.hken_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1109/EDSSC.2005.1635221en_US
dc.identifier.scopuseid_2-s2.0-43549114488en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-43549114488&selection=ref&src=s&origin=recordpageen_US
dc.identifier.spage123en_US
dc.identifier.epage126en_US
dc.identifier.scopusauthoridZou, X=23020170400en_US
dc.identifier.scopusauthoridLi, CX=13906721600en_US
dc.identifier.scopusauthoridXu, JP=35754128700en_US
dc.identifier.scopusauthoridLai, PT=7202946460en_US
dc.identifier.scopusauthoridChen, WB=51563508300en_US

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