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Conference Paper: Thermal modeling of on-chip interconnects and 3D packaging using EM tools

TitleThermal modeling of on-chip interconnects and 3D packaging using EM tools
Authors
Jiang, LKolluri, SRubin, BJSmith, HColgan, EGScheuermann, MRWakit, JADeutsch, AGill, J
Issue Date2008
Citation
Electrical Performance Of Electronic Packaging, Epep, 2008, p. 279-282 How to Cite?
DOI: http://dx.doi.org/10.1109/EPEP.2008.4675934
AbstractThe green (low power) chip design demands dramatic thermal and electrical simulation capabilities. In this paper, a novel thermal simulation approach for automatic thermal modeling of very large problems is introduced. This methodology can be fully integrated with existing solvers for electrical simulations, and make it possible to analyze practical on-chip and packaging thermal problems using the existing electromagnetic tools and geometry definitions, with very small additional effort. Its various applications to BEOL (on-chip wiring), thermal guideline design, and 3D integration (for multiple chip stacks) thermal modeling are investigated in this paper. We will demonstrate this capability with an automatic modeling framework, ChipJoule, for representative cases. © 2008 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/158571
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorJiang, Len_US
dc.contributor.authorKolluri, Sen_US
dc.contributor.authorRubin, BJen_US
dc.contributor.authorSmith, Hen_US
dc.contributor.authorColgan, EGen_US
dc.contributor.authorScheuermann, MRen_US
dc.contributor.authorWakit, JAen_US
dc.contributor.authorDeutsch, Aen_US
dc.contributor.authorGill, Jen_US
dc.date.accessioned2012-08-08T09:00:18Z-
dc.date.available2012-08-08T09:00:18Z-
dc.date.issued2008en_US
dc.identifier.citationElectrical Performance Of Electronic Packaging, Epep, 2008, p. 279-282en_US
dc.identifier.urihttp://hdl.handle.net/10722/158571-
dc.description.abstractThe green (low power) chip design demands dramatic thermal and electrical simulation capabilities. In this paper, a novel thermal simulation approach for automatic thermal modeling of very large problems is introduced. This methodology can be fully integrated with existing solvers for electrical simulations, and make it possible to analyze practical on-chip and packaging thermal problems using the existing electromagnetic tools and geometry definitions, with very small additional effort. Its various applications to BEOL (on-chip wiring), thermal guideline design, and 3D integration (for multiple chip stacks) thermal modeling are investigated in this paper. We will demonstrate this capability with an automatic modeling framework, ChipJoule, for representative cases. © 2008 IEEE.en_US
dc.languageengen_US
dc.relation.ispartofElectrical Performance of Electronic Packaging, EPEPen_US
dc.titleThermal modeling of on-chip interconnects and 3D packaging using EM toolsen_US
dc.typeConference_Paperen_US
dc.identifier.emailJiang, L:ljiang@eee.hku.hken_US
dc.identifier.authorityJiang, L=rp01338en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1109/EPEP.2008.4675934en_US
dc.identifier.scopuseid_2-s2.0-58049093680en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-58049093680&selection=ref&src=s&origin=recordpageen_US
dc.identifier.spage279en_US
dc.identifier.epage282en_US
dc.identifier.scopusauthoridJiang, L=36077777200en_US
dc.identifier.scopusauthoridKolluri, S=24724435100en_US
dc.identifier.scopusauthoridRubin, BJ=7201761344en_US
dc.identifier.scopusauthoridSmith, H=7406226774en_US
dc.identifier.scopusauthoridColgan, EG=7004998698en_US
dc.identifier.scopusauthoridScheuermann, MR=6701797634en_US
dc.identifier.scopusauthoridWakit, JA=52964871300en_US
dc.identifier.scopusauthoridDeutsch, A=7102025083en_US
dc.identifier.scopusauthoridGill, J=36820932600en_US

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