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Conference Paper: A model for matrix multiplication performance on FPGAs

TitleA model for matrix multiplication performance on FPGAs
Authors
Lin, CYSo, HKHLeong, PHW
KeywordsAnalytic models
Computational resources
Dense matrices
Future technologies
I/O bandwidth
Issue Date2011
PublisherIEEE, Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001053
Citation
The 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Greece, 5-7 September 2011. In Proceedings of the 21st FPL, 2011, p. 305-310 How to Cite?
DOI: http://dx.doi.org/10.1109/FPL.2011.62
AbstractComputations involving matrices form the kernel of a large spectrum of computationally demanding applications for which FPGAs have been utilized as accelerators. Their performance is related to their underlying architectural and system parameters such as computational resources, memory and I/O bandwidth. A simple analytic model that gives an estimate of the performance of FPGA-based sparse matrixvector and matrix-matrix multiplication is presented, dense matrix multiplication being a special case. The efficiency of existing implementations are compared to the model and performance trends for future technologies examined. © 2011 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/158736
ISBN
978-0-7695-4529-5
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorLin, CYen_US
dc.contributor.authorSo, HKHen_US
dc.contributor.authorLeong, PHWen_US
dc.date.accessioned2012-08-08T09:01:05Z-
dc.date.available2012-08-08T09:01:05Z-
dc.date.issued2011en_US
dc.identifier.citationThe 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Greece, 5-7 September 2011. In Proceedings of the 21st FPL, 2011, p. 305-310en_US
dc.identifier.isbn978-0-7695-4529-5-
dc.identifier.urihttp://hdl.handle.net/10722/158736-
dc.description.abstractComputations involving matrices form the kernel of a large spectrum of computationally demanding applications for which FPGAs have been utilized as accelerators. Their performance is related to their underlying architectural and system parameters such as computational resources, memory and I/O bandwidth. A simple analytic model that gives an estimate of the performance of FPGA-based sparse matrixvector and matrix-matrix multiplication is presented, dense matrix multiplication being a special case. The efficiency of existing implementations are compared to the model and performance trends for future technologies examined. © 2011 IEEE.en_US
dc.languageengen_US
dc.publisherIEEE, Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001053-
dc.relation.ispartofInternational Conference on Field Programmable Logic and Applications Proceedingsen_US
dc.subjectAnalytic models-
dc.subjectComputational resources-
dc.subjectDense matrices-
dc.subjectFuture technologies-
dc.subjectI/O bandwidth-
dc.titleA model for matrix multiplication performance on FPGAsen_US
dc.typeConference_Paperen_US
dc.identifier.emailLin, CY: colinfat@hku.hken_US
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hk-
dc.identifier.emailLeong, PHW: philip.leong@sydney.edu.au-
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1109/FPL.2011.62en_US
dc.identifier.scopuseid_2-s2.0-80455168428en_US
dc.identifier.hkuros207670-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-80455168428&selection=ref&src=s&origin=recordpageen_US
dc.identifier.spage305en_US
dc.identifier.epage310en_US
dc.publisher.placeUnited states-
dc.description.otherThe 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Greece, 5-7 September 2011. In Proceedings of the 21st FPL, 2011, p. 305-310-
dc.identifier.scopusauthoridLeong, PHW=7005928205en_US
dc.identifier.scopusauthoridSo, HKH=10738896800en_US
dc.identifier.scopusauthoridLin, CY=35177986900en_US

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