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Conference Paper: Computational Imaging Technology for Nanolithography

TitleComputational Imaging Technology for Nanolithography
Authors
Issue Date2013
PublisherThe Japan Society of Applied Physics (JSAP).
Citation
The Japan Society of Applied Physics (JSAP) - Optical Society of America (OSA) Joint Symposia at the 74th Japan Society of Applied Physics (JSAP) Autumn Meeting, Kyoto, Japan, 16-20 September 2013, p. 128, abstract no. 17p-D5-10 How to Cite?
AbstractThe rapid advancement of modern electronic technology is founded on Moore’s Law, which stipulates an exponential increase in transistor densities, leading to more and more functionalities in an integrated circuit (IC). A critical challenge in IC manufacturing lies in the nanolithography process, where the circuit pattern on a wafer is imprinted through imaging a photomask. Because of the small feature size compared with the wavelength of the light source, image distortion is significant due to diffraction and other aberrations. Computational technology, together with the modeling of the imaging process, is now an essential process to design the source and mask patterns that can counteract the distortions and allow for the printing of small features.
DescriptionSession: Information Photonics
Persistent Identifierhttp://hdl.handle.net/10722/201234

 

DC FieldValueLanguage
dc.contributor.authorLam, EYMen_US
dc.date.accessioned2014-08-21T07:18:19Z-
dc.date.available2014-08-21T07:18:19Z-
dc.date.issued2013en_US
dc.identifier.citationThe Japan Society of Applied Physics (JSAP) - Optical Society of America (OSA) Joint Symposia at the 74th Japan Society of Applied Physics (JSAP) Autumn Meeting, Kyoto, Japan, 16-20 September 2013, p. 128, abstract no. 17p-D5-10en_US
dc.identifier.urihttp://hdl.handle.net/10722/201234-
dc.descriptionSession: Information Photonics-
dc.description.abstractThe rapid advancement of modern electronic technology is founded on Moore’s Law, which stipulates an exponential increase in transistor densities, leading to more and more functionalities in an integrated circuit (IC). A critical challenge in IC manufacturing lies in the nanolithography process, where the circuit pattern on a wafer is imprinted through imaging a photomask. Because of the small feature size compared with the wavelength of the light source, image distortion is significant due to diffraction and other aberrations. Computational technology, together with the modeling of the imaging process, is now an essential process to design the source and mask patterns that can counteract the distortions and allow for the printing of small features.-
dc.languageengen_US
dc.publisherThe Japan Society of Applied Physics (JSAP).-
dc.relation.ispartofJapan Society of Applied Physics (JSAP) - Optical Society of America (OSA) Joint Symposiaen_US
dc.titleComputational Imaging Technology for Nanolithographyen_US
dc.typeConference_Paperen_US
dc.identifier.emailLam, EYM: elam@eee.hku.hken_US
dc.identifier.authorityLam, EYM=rp00131en_US
dc.identifier.hkuros233724en_US
dc.identifier.spage128, abstract no. 17p-D5-10-
dc.identifier.epage128, abstract no. 17p-D5-10-
dc.publisher.placeJapan-

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