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- Publisher Website: 10.1109/FCCM.2013.21
- Scopus: eid_2-s2.0-84881129674
- WOS: WOS:000326442500040
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Conference Paper: A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency
Title | A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency |
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Authors | |
Keywords | Coarse-grained reconfigurable arrays Design productivity FPGA implementations Hardware engineering High level applications High-level synthesis Operation scheduling Performance problems |
Issue Date | 2013 |
Publisher | IEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289 |
Citation | The 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA., 28-30 April 2013. In Conference Proceedings, 2013, p. 228-228 How to Cite? |
Abstract | Compared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often lack the intimate hardware engineering experience that is needed to achieve high performance on FPGAs, therefore undermining their usefulness as accelerators. To address the productivity and performance problems, a HLS methodology that utilizes soft coarse-grained reconfigurable arrays (SCGRAs) as an intermediate compilation step is presented. Instead of compiling high-level applications directly to circuits, the compilation process is reduced to an operation scheduling task targeting the SCGRA. © 2013 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/202275 |
ISBN | |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Liu, C | - |
dc.contributor.author | Lin, CY | - |
dc.contributor.author | So, HKH | - |
dc.date.accessioned | 2014-09-02T08:47:53Z | - |
dc.date.available | 2014-09-02T08:47:53Z | - |
dc.date.issued | 2013 | - |
dc.identifier.citation | The 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA., 28-30 April 2013. In Conference Proceedings, 2013, p. 228-228 | - |
dc.identifier.isbn | 978-0-7695-4969-9 | - |
dc.identifier.uri | http://hdl.handle.net/10722/202275 | - |
dc.description.abstract | Compared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often lack the intimate hardware engineering experience that is needed to achieve high performance on FPGAs, therefore undermining their usefulness as accelerators. To address the productivity and performance problems, a HLS methodology that utilizes soft coarse-grained reconfigurable arrays (SCGRAs) as an intermediate compilation step is presented. Instead of compiling high-level applications directly to circuits, the compilation process is reduced to an operation scheduling task targeting the SCGRA. © 2013 IEEE. | - |
dc.language | eng | - |
dc.publisher | IEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289 | - |
dc.relation.ispartof | Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) Proceedings | - |
dc.subject | Coarse-grained reconfigurable arrays | - |
dc.subject | Design productivity | - |
dc.subject | FPGA implementations | - |
dc.subject | Hardware engineering | - |
dc.subject | High level applications | - |
dc.subject | High-level synthesis | - |
dc.subject | Operation scheduling | - |
dc.subject | Performance problems | - |
dc.title | A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency | en_US |
dc.type | Conference_Paper | en_US |
dc.identifier.email | So, HKH: skhay@hkucc.hku.hk | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/FCCM.2013.21 | - |
dc.identifier.scopus | eid_2-s2.0-84881129674 | - |
dc.identifier.hkuros | 236890 | - |
dc.identifier.spage | 228 | - |
dc.identifier.epage | 228 | - |
dc.identifier.isi | WOS:000326442500040 | - |
dc.publisher.place | United States | - |
dc.customcontrol.immutable | sml 140902 | - |