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Article: Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

TitleImproved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory
Authors
Chen, JXXu, JPLiu, LHuang, XDLai, PT
Issue Date2014
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2014, v. 54 n. 2, p. 393-396 How to Cite?
DOI: http://dx.doi.org/10.1016/j.microrel.2013.10.011
Persistent Identifierhttp://hdl.handle.net/10722/202923
ISSN
0026-2714
2021 Impact Factor: 1.418
2020 SCImago Journal Rankings: 0.445
ISI Accession Number ID
WOS:000332433600010

 

DC FieldValueLanguage
dc.contributor.authorChen, JXen_US
dc.contributor.authorXu, JPen_US
dc.contributor.authorLiu, Len_US
dc.contributor.authorHuang, XDen_US
dc.contributor.authorLai, PTen_US
dc.date.accessioned2014-09-19T10:10:18Z-
dc.date.available2014-09-19T10:10:18Z-
dc.date.issued2014en_US
dc.identifier.citationMicroelectronics Reliability, 2014, v. 54 n. 2, p. 393-396en_US
dc.identifier.issn0026-2714-
dc.identifier.urihttp://hdl.handle.net/10722/202923-
dc.languageengen_US
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel-
dc.relation.ispartofMicroelectronics Reliabilityen_US
dc.rightsNOTICE: this is the author’s version of a work that was accepted for publication in Microelectronics Reliability. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Microelectronics Reliability, 2014, v. 54 n. 2, p. 393-396. DOI: 10.1016/j.microrel.2013.10.011-
dc.rightsThis work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.-
dc.titleImproved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memoryen_US
dc.typeArticleen_US
dc.identifier.emailChen, JX: cjxhk@hku.hken_US
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_US
dc.identifier.emailLiu, L: liulu@hku.hken_US
dc.identifier.emailLai, PT: laip@eee.hku.hken_US
dc.identifier.authorityXu, JP=rp00197en_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturepostprint-
dc.identifier.doi10.1016/j.microrel.2013.10.011-
dc.identifier.scopuseid_2-s2.0-84894899241-
dc.identifier.hkuros240521en_US
dc.identifier.volume54en_US
dc.identifier.issue2-
dc.identifier.spage393en_US
dc.identifier.epage396en_US
dc.identifier.isiWOS:000332433600010-
dc.publisher.placeUnited Kingdom-
dc.identifier.issnl0026-2714-

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