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- Publisher Website: 10.1145/2593069.2593087
- Scopus: eid_2-s2.0-84903150190
- WOS: WOS:000346506400115
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Conference Paper: An Efficient Two-level DC Operating Points Finder for Transistor Circuits
Title | An Efficient Two-level DC Operating Points Finder for Transistor Circuits |
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Authors | |
Keywords | DC analysis nonlinear equations transistor circuits simulation inclusion method |
Issue Date | 2014 |
Publisher | Association for Computing Machinery (ACM). The Journal's web site is located at https://dl.acm.org/conference/dac/proceedings |
Citation | Proceedings of the 51st Annual Design Automation Conference (DAC14), San Francisco, USA, 2-5 June 2014, p. 1-6 How to Cite? |
Abstract | DC analysis, as a foundation for the simulation of many electronic circuits, is concerned with locating DC operating points. In this paper, a new and efficient algorithm to find all DC operating points is proposed for transistor circuits. The novelty of this DC operating points finder is its two-level simple implementation based on the affine arithmetic preconditioning and interval contraction method. Compared to traditional methods such as homotopy, this finder offers a dramatically faster way of computing all roots, without sacrificing any accuracy. Explicit numerical examples and comparative analysis are given to demonstrate the feasibility and accuracy of the proposed approach. |
Persistent Identifier | http://hdl.handle.net/10722/204079 |
ISBN | |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Deng, J | - |
dc.contributor.author | Batselier, K | - |
dc.contributor.author | Zhang, Y | - |
dc.contributor.author | Wong, N | - |
dc.date.accessioned | 2014-09-19T20:04:40Z | - |
dc.date.available | 2014-09-19T20:04:40Z | - |
dc.date.issued | 2014 | - |
dc.identifier.citation | Proceedings of the 51st Annual Design Automation Conference (DAC14), San Francisco, USA, 2-5 June 2014, p. 1-6 | - |
dc.identifier.isbn | 9781450327305 | - |
dc.identifier.uri | http://hdl.handle.net/10722/204079 | - |
dc.description.abstract | DC analysis, as a foundation for the simulation of many electronic circuits, is concerned with locating DC operating points. In this paper, a new and efficient algorithm to find all DC operating points is proposed for transistor circuits. The novelty of this DC operating points finder is its two-level simple implementation based on the affine arithmetic preconditioning and interval contraction method. Compared to traditional methods such as homotopy, this finder offers a dramatically faster way of computing all roots, without sacrificing any accuracy. Explicit numerical examples and comparative analysis are given to demonstrate the feasibility and accuracy of the proposed approach. | - |
dc.language | eng | - |
dc.publisher | Association for Computing Machinery (ACM). The Journal's web site is located at https://dl.acm.org/conference/dac/proceedings | - |
dc.relation.ispartof | Proceedings of the 51st Annual Design Automation Conference (DAC) | - |
dc.subject | DC analysis | - |
dc.subject | nonlinear equations | - |
dc.subject | transistor circuits simulation | - |
dc.subject | inclusion method | - |
dc.title | An Efficient Two-level DC Operating Points Finder for Transistor Circuits | - |
dc.type | Conference_Paper | - |
dc.identifier.email | Batselier, K: kbatseli@hku.hk | - |
dc.identifier.email | Zhang, Y: yangzh@hku.hk | - |
dc.identifier.email | Wong, N: nwong@eee.hku.hk | - |
dc.identifier.authority | Wong, N=rp00190 | - |
dc.identifier.doi | 10.1145/2593069.2593087 | - |
dc.identifier.scopus | eid_2-s2.0-84903150190 | - |
dc.identifier.hkuros | 238585 | - |
dc.identifier.hkuros | 236712 | - |
dc.identifier.spage | 1 | - |
dc.identifier.epage | 6 | - |
dc.identifier.isi | WOS:000346506400115 | - |
dc.publisher.place | United States | - |