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- Publisher Website: 10.1109/TCSI.2016.2607227
- Scopus: eid_2-s2.0-85011702123
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Article: Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Title | Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division |
---|---|
Authors | |
Keywords | Arithmetic ASIC configurable architecture dual-mode division floating point division multi-precision arithmetic |
Issue Date | 2017 |
Publisher | IEEE. The Journal's web site is located at http://tcas1.polito.it/ |
Citation | IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, v. 64, p. 386-398 How to Cite? |
Persistent Identifier | http://hdl.handle.net/10722/234045 |
ISSN | 2023 Impact Factor: 5.2 2023 SCImago Journal Rankings: 1.836 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Jaiswal, MK | - |
dc.contributor.author | So, HKH | - |
dc.date.accessioned | 2016-10-14T06:58:42Z | - |
dc.date.available | 2016-10-14T06:58:42Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, v. 64, p. 386-398 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10722/234045 | - |
dc.language | eng | - |
dc.publisher | IEEE. The Journal's web site is located at http://tcas1.polito.it/ | - |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I: Regular Papers | - |
dc.rights | IEEE Transactions on Circuits and Systems I: Regular Papers. Copyright © IEEE. | - |
dc.rights | ©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.subject | Arithmetic | - |
dc.subject | ASIC | - |
dc.subject | configurable architecture | - |
dc.subject | dual-mode division | - |
dc.subject | floating point division | - |
dc.subject | multi-precision arithmetic | - |
dc.title | Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division | - |
dc.type | Article | - |
dc.identifier.email | Jaiswal, MK: manishkj@hku.hk | - |
dc.identifier.email | So, HKH: hso@eee.hku.hk | - |
dc.identifier.authority | So, HKH=rp00169 | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/TCSI.2016.2607227 | - |
dc.identifier.scopus | eid_2-s2.0-85011702123 | - |
dc.identifier.hkuros | 280262 | - |
dc.identifier.hkuros | 267491 | - |
dc.identifier.volume | 64 | - |
dc.identifier.spage | 386 | - |
dc.identifier.epage | 398 | - |
dc.identifier.isi | WOS:000395487900012 | - |
dc.publisher.place | United States | - |
dc.identifier.issnl | 1549-8328 | - |