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- Publisher Website: 10.1109/FPL.2016.7577360
- Scopus: eid_2-s2.0-84994802529
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Conference Paper: GraVF: a vertex-centric distributed graph processing framework on FPGAs
Title | GraVF: a vertex-centric distributed graph processing framework on FPGAs |
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Authors | |
Issue Date | 2016 |
Publisher | IEEE. The Proceedings' web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001053 |
Citation | The 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland, 29 August-2 September 2016. In Conference Proceedings, 2016, article no. 7577360 How to Cite? |
Abstract | FPGAs are promising platforms to efficiently execute distributed graph algorithms. Unfortunately, they are notoriously hard to program, especially when the problem size and system complexity increases. In this paper, we propose GraVF, a high-level design framework for distributed graph processing on FPGAs. It leverages the vertex-centric paradigm, which is naturally distributed and requires the user to define only very small kernels and their associated message semantics for the target application. The user design may subsequently be elaborated and compiled to the target system automatically by the framework. To demonstrate the flexibility and capabilities of the proposed framework, 4 graph algorithms with distinct requirements have been implemented, namely breadth-first search, PageRank, single source shortest path, and connected component. Results show that the proposed framework is capable of producing FPGA designs with performance comparable to similar custom designs while requiring only minimal input from the user. © 2016 EPFL. |
Persistent Identifier | http://hdl.handle.net/10722/234982 |
ISBN | |
ISSN | |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Engelhardt, N | - |
dc.contributor.author | So, HKH | - |
dc.date.accessioned | 2016-10-14T13:50:31Z | - |
dc.date.available | 2016-10-14T13:50:31Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | The 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland, 29 August-2 September 2016. In Conference Proceedings, 2016, article no. 7577360 | - |
dc.identifier.isbn | 978-283991844-2 | - |
dc.identifier.issn | 1946-1488 | - |
dc.identifier.uri | http://hdl.handle.net/10722/234982 | - |
dc.description.abstract | FPGAs are promising platforms to efficiently execute distributed graph algorithms. Unfortunately, they are notoriously hard to program, especially when the problem size and system complexity increases. In this paper, we propose GraVF, a high-level design framework for distributed graph processing on FPGAs. It leverages the vertex-centric paradigm, which is naturally distributed and requires the user to define only very small kernels and their associated message semantics for the target application. The user design may subsequently be elaborated and compiled to the target system automatically by the framework. To demonstrate the flexibility and capabilities of the proposed framework, 4 graph algorithms with distinct requirements have been implemented, namely breadth-first search, PageRank, single source shortest path, and connected component. Results show that the proposed framework is capable of producing FPGA designs with performance comparable to similar custom designs while requiring only minimal input from the user. © 2016 EPFL. | - |
dc.language | eng | - |
dc.publisher | IEEE. The Proceedings' web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001053 | - |
dc.relation.ispartof | 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 Proceedings | - |
dc.rights | 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 Proceedings. Copyright © IEEE. | - |
dc.rights | ©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.title | GraVF: a vertex-centric distributed graph processing framework on FPGAs | - |
dc.type | Conference_Paper | - |
dc.identifier.email | So, HKH: hso@eee.hku.hk | - |
dc.identifier.authority | So, HKH=rp00169 | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/FPL.2016.7577360 | - |
dc.identifier.scopus | eid_2-s2.0-84994802529 | - |
dc.identifier.hkuros | 268688 | - |
dc.identifier.hkuros | 281353 | - |
dc.identifier.isi | WOS:000386610400062 | - |
dc.publisher.place | United States | - |
dc.customcontrol.immutable | sml 161202 | - |
dc.identifier.issnl | 1946-147X | - |