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Conference Paper: Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

TitleConfigurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Authors
Jaiswal, MKCheung, RCCBalakrishnan, MPaul, K
KeywordsASIC
Dynamic Configurable Computing
Floating Point Division
Multi-precision Arithmetic
Issue Date2014
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807
Citation
Proceedings of 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, 9-11 July 2014, p. 332-337 How to Cite?
DOI: http://dx.doi.org/10.1109/ISVLSI.2014.45
Persistent Identifierhttp://hdl.handle.net/10722/249248
ISSN
2159-3469
2020 SCImago Journal Rankings: 0.226
ISI Accession Number ID
WOS:000361018000060

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorCheung, RCC-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorPaul, K-
dc.date.accessioned2017-11-08T07:33:50Z-
dc.date.available2017-11-08T07:33:50Z-
dc.date.issued2014-
dc.identifier.citationProceedings of 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, 9-11 July 2014, p. 332-337-
dc.identifier.issn2159-3469-
dc.identifier.urihttp://hdl.handle.net/10722/249248-
dc.languageeng-
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807-
dc.relation.ispartofIEEE Computer Society Annual Symposium on VLSI (ISVLSI)-
dc.rights©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectASIC-
dc.subjectDynamic Configurable Computing-
dc.subjectFloating Point Division-
dc.subjectMulti-precision Arithmetic-
dc.titleConfigurable Architecture for Double/Two-Parallel Single Precision Floating Point Division-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.description.naturepostprint-
dc.identifier.doi10.1109/ISVLSI.2014.45-
dc.identifier.scopuseid_2-s2.0-84908192206-
dc.identifier.hkuros280303-
dc.identifier.spage332-
dc.identifier.epage337-
dc.identifier.isiWOS:000361018000060-
dc.publisher.placeUnited States-
dc.identifier.issnl2159-3469-

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