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Article: A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization
Title | A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization |
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Authors | |
Keywords | Adaptive beamformer Approximation Array processing Division-free FPGA Variable regularization Variable step-size |
Issue Date | 2018 |
Publisher | Institute of Electrical and Electronics Engineers: Open Access Journals. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639 |
Citation | IEEE Access, 2018, v. 6, p. 64470-64485 How to Cite? |
Abstract | This paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new variable step-size least mean squares algorithm for complex input is proposed to further improve the convergence and the steady-state performance of the adaptive beamformer. Moreover, a variable regularization scheme is incorporated to mitigate possible signal cancellation due to possible mismatches in steering vector. Furthermore, a statistical analysis on the mean and mean squares convergence of the algorithm is performed and validated using Monte Carlo simulations. An efficient architecture of the proposed adaptive beamformer is also proposed for its real-time implementation. It employs a novel division-free approach by quantizing the normalization factor into a limited number of levels so that the division can be implemented using canonical signed digits, resulting in multiplier-less realization. The performance of the resultant division-free implementation can achieve similar convergence and steady-state performance as a conventional divider approach while achieving at least 21% less hardware resources and 26.85% higher operating speed in Xilinx Virtex7 (XC7VX330T) field programming gate array for an eight-sensor uniform linear array. Finally, the beam can be stabilized remarkably in only 1 μs at a system clock frequency of 124 MHz. |
Persistent Identifier | http://hdl.handle.net/10722/275027 |
ISSN | 2023 Impact Factor: 3.4 2023 SCImago Journal Rankings: 0.960 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Zhao, W | - |
dc.contributor.author | Lin, JQ | - |
dc.contributor.author | Chan, SC | - |
dc.contributor.author | So, HKH | - |
dc.date.accessioned | 2019-09-10T02:33:57Z | - |
dc.date.available | 2019-09-10T02:33:57Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | IEEE Access, 2018, v. 6, p. 64470-64485 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | http://hdl.handle.net/10722/275027 | - |
dc.description.abstract | This paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new variable step-size least mean squares algorithm for complex input is proposed to further improve the convergence and the steady-state performance of the adaptive beamformer. Moreover, a variable regularization scheme is incorporated to mitigate possible signal cancellation due to possible mismatches in steering vector. Furthermore, a statistical analysis on the mean and mean squares convergence of the algorithm is performed and validated using Monte Carlo simulations. An efficient architecture of the proposed adaptive beamformer is also proposed for its real-time implementation. It employs a novel division-free approach by quantizing the normalization factor into a limited number of levels so that the division can be implemented using canonical signed digits, resulting in multiplier-less realization. The performance of the resultant division-free implementation can achieve similar convergence and steady-state performance as a conventional divider approach while achieving at least 21% less hardware resources and 26.85% higher operating speed in Xilinx Virtex7 (XC7VX330T) field programming gate array for an eight-sensor uniform linear array. Finally, the beam can be stabilized remarkably in only 1 μs at a system clock frequency of 124 MHz. | - |
dc.language | eng | - |
dc.publisher | Institute of Electrical and Electronics Engineers: Open Access Journals. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639 | - |
dc.relation.ispartof | IEEE Access | - |
dc.rights | © 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. | - |
dc.subject | Adaptive beamformer | - |
dc.subject | Approximation | - |
dc.subject | Array processing | - |
dc.subject | Division-free | - |
dc.subject | FPGA | - |
dc.subject | Variable regularization | - |
dc.subject | Variable step-size | - |
dc.title | A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization | - |
dc.type | Article | - |
dc.identifier.email | Chan, SC: scchan@eee.hku.hk | - |
dc.identifier.email | So, HKH: hso@eee.hku.hk | - |
dc.identifier.authority | Chan, SC=rp00094 | - |
dc.identifier.authority | So, HKH=rp00169 | - |
dc.description.nature | published_or_final_version | - |
dc.identifier.doi | 10.1109/ACCESS.2018.2875409 | - |
dc.identifier.scopus | eid_2-s2.0-85054604157 | - |
dc.identifier.hkuros | 304151 | - |
dc.identifier.volume | 6 | - |
dc.identifier.spage | 64470 | - |
dc.identifier.epage | 64485 | - |
dc.identifier.isi | WOS:000452588300001 | - |
dc.publisher.place | United States | - |
dc.identifier.issnl | 2169-3536 | - |