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Article: A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization

TitleA Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization
Authors
KeywordsAdaptive beamformer
Approximation
Array processing
Division-free
FPGA
Variable regularization
Variable step-size
Issue Date2018
PublisherInstitute of Electrical and Electronics Engineers (IEEE): OAJ. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639
Citation
IEEE Access, 2018, v. 6, p. 64470-64485 How to Cite?
AbstractThis paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new variable step-size least mean squares algorithm for complex input is proposed to further improve the convergence and the steady-state performance of the adaptive beamformer. Moreover, a variable regularization scheme is incorporated to mitigate possible signal cancellation due to possible mismatches in steering vector. Furthermore, a statistical analysis on the mean and mean squares convergence of the algorithm is performed and validated using Monte Carlo simulations. An efficient architecture of the proposed adaptive beamformer is also proposed for its real-time implementation. It employs a novel division-free approach by quantizing the normalization factor into a limited number of levels so that the division can be implemented using canonical signed digits, resulting in multiplier-less realization. The performance of the resultant division-free implementation can achieve similar convergence and steady-state performance as a conventional divider approach while achieving at least 21% less hardware resources and 26.85% higher operating speed in Xilinx Virtex7 (XC7VX330T) field programming gate array for an eight-sensor uniform linear array. Finally, the beam can be stabilized remarkably in only 1 μs at a system clock frequency of 124 MHz.
Persistent Identifierhttp://hdl.handle.net/10722/275027
ISSN
2019 Impact Factor: 3.745
2015 SCImago Journal Rankings: 0.947
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorZhao, W-
dc.contributor.authorLin, JQ-
dc.contributor.authorChan, SC-
dc.contributor.authorSo, HKH-
dc.date.accessioned2019-09-10T02:33:57Z-
dc.date.available2019-09-10T02:33:57Z-
dc.date.issued2018-
dc.identifier.citationIEEE Access, 2018, v. 6, p. 64470-64485-
dc.identifier.issn2169-3536-
dc.identifier.urihttp://hdl.handle.net/10722/275027-
dc.description.abstractThis paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new variable step-size least mean squares algorithm for complex input is proposed to further improve the convergence and the steady-state performance of the adaptive beamformer. Moreover, a variable regularization scheme is incorporated to mitigate possible signal cancellation due to possible mismatches in steering vector. Furthermore, a statistical analysis on the mean and mean squares convergence of the algorithm is performed and validated using Monte Carlo simulations. An efficient architecture of the proposed adaptive beamformer is also proposed for its real-time implementation. It employs a novel division-free approach by quantizing the normalization factor into a limited number of levels so that the division can be implemented using canonical signed digits, resulting in multiplier-less realization. The performance of the resultant division-free implementation can achieve similar convergence and steady-state performance as a conventional divider approach while achieving at least 21% less hardware resources and 26.85% higher operating speed in Xilinx Virtex7 (XC7VX330T) field programming gate array for an eight-sensor uniform linear array. Finally, the beam can be stabilized remarkably in only 1 μs at a system clock frequency of 124 MHz.-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE): OAJ. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639-
dc.relation.ispartofIEEE Access-
dc.rights© 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.-
dc.subjectAdaptive beamformer-
dc.subjectApproximation-
dc.subjectArray processing-
dc.subjectDivision-free-
dc.subjectFPGA-
dc.subjectVariable regularization-
dc.subjectVariable step-size-
dc.titleA Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization-
dc.typeArticle-
dc.identifier.emailChan, SC: scchan@eee.hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authorityChan, SC=rp00094-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/ACCESS.2018.2875409-
dc.identifier.scopuseid_2-s2.0-85054604157-
dc.identifier.hkuros304151-
dc.identifier.volume6-
dc.identifier.spage64470-
dc.identifier.epage64485-
dc.identifier.isiWOS:000452588300001-
dc.publisher.placeUnited States-
dc.identifier.issnl2169-3536-

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