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Article: Effects of a Gate-Electrode/Gate-Dielectric Interlayer on Carrier Mobility for Pentacene Organic Thin-Film Transistors
Title | Effects of a Gate-Electrode/Gate-Dielectric Interlayer on Carrier Mobility for Pentacene Organic Thin-Film Transistors |
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Authors | |
Keywords | Logic gates Dielectrics Annealing Pentacene Organic thin film transistors |
Issue Date | 2018 |
Publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 |
Citation | IEEE Electron Device Letters, 2018, v. 39 n. 10, p. 1516-1519 How to Cite? |
Abstract | Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n + Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer. |
Persistent Identifier | http://hdl.handle.net/10722/278165 |
ISSN | 2023 Impact Factor: 4.1 2023 SCImago Journal Rankings: 1.250 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | MA, YX | - |
dc.contributor.author | TANG, WM | - |
dc.contributor.author | Lai, PT | - |
dc.date.accessioned | 2019-10-04T08:08:44Z | - |
dc.date.available | 2019-10-04T08:08:44Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | IEEE Electron Device Letters, 2018, v. 39 n. 10, p. 1516-1519 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10722/278165 | - |
dc.description.abstract | Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n + Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer. | - |
dc.language | eng | - |
dc.publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 | - |
dc.relation.ispartof | IEEE Electron Device Letters | - |
dc.rights | IEEE Electron Device Letters. Copyright © IEEE. | - |
dc.rights | ©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.subject | Logic gates | - |
dc.subject | Dielectrics | - |
dc.subject | Annealing | - |
dc.subject | Pentacene | - |
dc.subject | Organic thin film transistors | - |
dc.title | Effects of a Gate-Electrode/Gate-Dielectric Interlayer on Carrier Mobility for Pentacene Organic Thin-Film Transistors | - |
dc.type | Article | - |
dc.identifier.email | Lai, PT: laip@eee.hku.hk | - |
dc.identifier.authority | Lai, PT=rp00130 | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/LED.2018.2867193 | - |
dc.identifier.scopus | eid_2-s2.0-85052698153 | - |
dc.identifier.hkuros | 306906 | - |
dc.identifier.volume | 39 | - |
dc.identifier.issue | 10 | - |
dc.identifier.spage | 1516 | - |
dc.identifier.epage | 1519 | - |
dc.identifier.isi | WOS:000446449300008 | - |
dc.publisher.place | United States | - |
dc.identifier.issnl | 0741-3106 | - |