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- Publisher Website: 10.1109/EDSSC.2017.8126502
- Scopus: eid_2-s2.0-85043489987
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Conference Paper: Fabrication and electrical performance of CVD-grown MoS2 transistor
Title | Fabrication and electrical performance of CVD-grown MoS2 transistor |
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Authors | |
Keywords | Buffer layer Carrier mobility CVD MoS2 transistor |
Issue Date | 2017 |
Publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853 |
Citation | 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 18-20 October 2017, p. 1-3 How to Cite? |
Abstract | A 6-layer continuous and uniform MoS 2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS 2 transistor are investigated, and enhanced carrier mobility (0.69 cm 2 /V·s) is achieved by using Ta 2 O 5 as the buffer layer. |
Persistent Identifier | http://hdl.handle.net/10722/278340 |
ISBN |
DC Field | Value | Language |
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dc.contributor.author | Wen, M | - |
dc.contributor.author | Xu, JP | - |
dc.contributor.author | Liu, L | - |
dc.contributor.author | Zhao, X | - |
dc.contributor.author | Lai, PT | - |
dc.contributor.author | Tang, WM | - |
dc.date.accessioned | 2019-10-04T08:12:06Z | - |
dc.date.available | 2019-10-04T08:12:06Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 18-20 October 2017, p. 1-3 | - |
dc.identifier.isbn | 978-1-5386-2908-6 | - |
dc.identifier.uri | http://hdl.handle.net/10722/278340 | - |
dc.description.abstract | A 6-layer continuous and uniform MoS 2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS 2 transistor are investigated, and enhanced carrier mobility (0.69 cm 2 /V·s) is achieved by using Ta 2 O 5 as the buffer layer. | - |
dc.language | eng | - |
dc.publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853 | - |
dc.relation.ispartof | IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) | - |
dc.rights | IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). Copyright © IEEE. | - |
dc.rights | ©2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.subject | Buffer layer | - |
dc.subject | Carrier mobility | - |
dc.subject | CVD | - |
dc.subject | MoS2 transistor | - |
dc.title | Fabrication and electrical performance of CVD-grown MoS2 transistor | - |
dc.type | Conference_Paper | - |
dc.identifier.email | Lai, PT: laip@eee.hku.hk | - |
dc.identifier.authority | Lai, PT=rp00130 | - |
dc.identifier.doi | 10.1109/EDSSC.2017.8126502 | - |
dc.identifier.scopus | eid_2-s2.0-85043489987 | - |
dc.identifier.hkuros | 306917 | - |
dc.identifier.spage | 1 | - |
dc.identifier.epage | 3 | - |
dc.publisher.place | United States | - |