Positive bias-induced V<inf>th</inf> instability in graphene field effect transistors

Abstract

In this letter, we report positive bias-induced V th instability in single-and multilayer graphene field effect transistors (GFETs) with back-gate SiO 2 dielectric. The Δ V th of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, it does not show much dependence on gate length, width, and the number of graphene layers. The 1/f noise measurement indicates no newly generated traps in SiO 2 interface caused by positive bias stressing. Mobility is seen to degrade with temperature increasing. The degradation is believed to be caused by the trapped electrons in bulk SiO 2 or SiO 2 interface and trap generation in bulk SiO 2. © 2012 IEEE.