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Article: Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

TitleDamage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors
Authors
Keywordsinterface properties
mica dielectric
mobility
multilayer MoS2
top-gated transistors
Issue Date2019
PublisherInstitute of Physics Publishing. The Journal's web site is located at http://www.iop.org/journals/nano
Citation
Nanotechnology, 2019, v. 30 n. 34, p. article no. 345204 How to Cite?
AbstractFor top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ~108, a low threshold voltage of ~0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.
Persistent Identifierhttp://hdl.handle.net/10722/287655
ISSN
2019 Impact Factor: 3.551
2015 SCImago Journal Rankings: 1.196
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorZou, X-
dc.contributor.authorXu, J-
dc.contributor.authorLiu, L-
dc.contributor.authorWang, H-
dc.contributor.authorLai, PT-
dc.contributor.authorTang, WM-
dc.date.accessioned2020-10-05T12:01:17Z-
dc.date.available2020-10-05T12:01:17Z-
dc.date.issued2019-
dc.identifier.citationNanotechnology, 2019, v. 30 n. 34, p. article no. 345204-
dc.identifier.issn0957-4484-
dc.identifier.urihttp://hdl.handle.net/10722/287655-
dc.description.abstractFor top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ~108, a low threshold voltage of ~0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.-
dc.languageeng-
dc.publisherInstitute of Physics Publishing. The Journal's web site is located at http://www.iop.org/journals/nano-
dc.relation.ispartofNanotechnology-
dc.rightsNanotechnology. Copyright © Institute of Physics Publishing.-
dc.rightsThis is an author-created, un-copyedited version of an article published in [insert name of journal]. IOP Publishing Ltd is not responsible for any errors or omissions in this version of the manuscript or any version derived from it. The Version of Record is available online at http://dx.doi.org/[insert DOI].-
dc.subjectinterface properties-
dc.subjectmica dielectric-
dc.subjectmobility-
dc.subjectmultilayer MoS2-
dc.subjecttop-gated transistors-
dc.titleDamage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors-
dc.typeArticle-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1088/1361-6528/ab1ff3-
dc.identifier.pmid31067521-
dc.identifier.scopuseid_2-s2.0-85069518289-
dc.identifier.scopuseid_2-s2.0-85069518289-
dc.identifier.hkuros315171-
dc.identifier.volume30-
dc.identifier.issue34-
dc.identifier.spagearticle no. 345204-
dc.identifier.epagearticle no. 345204-
dc.identifier.isiWOS:000470705900002-
dc.publisher.placeUnited Kingdom-
dc.identifier.issnl0957-4484-

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