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Conference Paper: CSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks

TitleCSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks
Authors
KeywordsFPGA
RNN
structured pruning
workload balancing
Issue Date2020
PublisherAssociation for Computing Machinery (ACM).
Citation
Proceedings of the 34th ACM International Conference on Supercomputing (ICS 2020), Barcelona Spain, 29 June - 2 July 2020, Article No. 24: 1-12 How to Cite?
AbstractRecurrent neural networks (RNNs) have been widely adopted in temporal sequence analysis, where realtime performance is often in demand. However, RNNs suffer from heavy computational workload as the model often comes with large weight matrices. Pruning (a model compression method) schemes have been proposed for RNNs to eliminate the redundant (close-to-zero) weight values. On one hand, the non-structured pruning methods achieve a high pruning rate but introducing computation irregularity (random sparsity), which is unfriendly to parallel hardware. On the other hand, hardware-oriented structured pruning suffers from low pruning rate due to restricted constraints on allowable pruning structure. This paper presents CSB-RNN, an optimized full-stack RNN framework with a novel compressed structured block (CSB) pruning technique. The CSB pruned RNN model comes with both fine pruning granularity that facilitates a high pruning rate and regular structure that benefits the hardware parallelism. To address the challenges in parallelizing the CSB pruned model inference with fine-grained structural sparsity, we propose a novel hardware architecture with a dedicated compiler. Gaining from the architecture-compilation co-design, the hardware not only supports various RNN cell types, but is also able to address the challenging workload imbalance issue and therefore significantly improves the hardware efficiency (utilization). Compared to the vanilla design without optimizations, the hardware utilization has been enhanced by over 2X. With experiments on 10 RNN models from multiple application domains, CSB pruning demonstrates 3.5X-25X lossless pruning rate, which is 1.6X to 3.9X over existing designs. With several other innovations applied, the CSB-RNN inference can achieve faster-than-realtime latency of 0.79μs-6.58μs in an FPGA implementation, which contributes to 1.12X-12.57X lower latency and 3.53X-58.89X improvement on power-efficiency over the state-of-the-art.
DescriptionSession 6: Architecture II
Persistent Identifierhttp://hdl.handle.net/10722/288469
ISBN

 

DC FieldValueLanguage
dc.contributor.authorShi, R-
dc.contributor.authorDong, P-
dc.contributor.authorGeng, T-
dc.contributor.authorDing, Y-
dc.contributor.authorMa, X-
dc.contributor.authorSo, HKH-
dc.contributor.authorHerbordt, M-
dc.contributor.authorLi, A-
dc.contributor.authorWang, Y-
dc.date.accessioned2020-10-05T12:13:22Z-
dc.date.available2020-10-05T12:13:22Z-
dc.date.issued2020-
dc.identifier.citationProceedings of the 34th ACM International Conference on Supercomputing (ICS 2020), Barcelona Spain, 29 June - 2 July 2020, Article No. 24: 1-12-
dc.identifier.isbn9781450379830-
dc.identifier.urihttp://hdl.handle.net/10722/288469-
dc.descriptionSession 6: Architecture II-
dc.description.abstractRecurrent neural networks (RNNs) have been widely adopted in temporal sequence analysis, where realtime performance is often in demand. However, RNNs suffer from heavy computational workload as the model often comes with large weight matrices. Pruning (a model compression method) schemes have been proposed for RNNs to eliminate the redundant (close-to-zero) weight values. On one hand, the non-structured pruning methods achieve a high pruning rate but introducing computation irregularity (random sparsity), which is unfriendly to parallel hardware. On the other hand, hardware-oriented structured pruning suffers from low pruning rate due to restricted constraints on allowable pruning structure. This paper presents CSB-RNN, an optimized full-stack RNN framework with a novel compressed structured block (CSB) pruning technique. The CSB pruned RNN model comes with both fine pruning granularity that facilitates a high pruning rate and regular structure that benefits the hardware parallelism. To address the challenges in parallelizing the CSB pruned model inference with fine-grained structural sparsity, we propose a novel hardware architecture with a dedicated compiler. Gaining from the architecture-compilation co-design, the hardware not only supports various RNN cell types, but is also able to address the challenging workload imbalance issue and therefore significantly improves the hardware efficiency (utilization). Compared to the vanilla design without optimizations, the hardware utilization has been enhanced by over 2X. With experiments on 10 RNN models from multiple application domains, CSB pruning demonstrates 3.5X-25X lossless pruning rate, which is 1.6X to 3.9X over existing designs. With several other innovations applied, the CSB-RNN inference can achieve faster-than-realtime latency of 0.79μs-6.58μs in an FPGA implementation, which contributes to 1.12X-12.57X lower latency and 3.53X-58.89X improvement on power-efficiency over the state-of-the-art.-
dc.languageeng-
dc.publisherAssociation for Computing Machinery (ACM).-
dc.relation.ispartofProceedings of the 34th ACM International Conference on Supercomputing (ICS 2020)-
dc.subjectFPGA-
dc.subjectRNN-
dc.subjectstructured pruning-
dc.subjectworkload balancing-
dc.titleCSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks-
dc.typeConference_Paper-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1145/3392717.3392749-
dc.identifier.scopuseid_2-s2.0-85088517313-
dc.identifier.hkuros315356-
dc.publisher.placeNew York, NY-

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