A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks

Abstract

We present an in-memory accelerator circuit design for ResNet-50, a large-scale residual neural network with 49 convolutional layers, 2.6 × 10 7 parameters and 4.1 × 10 9 floating-point operations (FLOPS). A 4-bit quantized ResNet-50 is first chosen among various bitwidths for the best trade-off. It is then trained and fully mapped onto a 4608 × 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top-5 accuracy on ImageNet, only 2.5% lower than the full-precision original. Two versatile CMOS 4-bit DAC and ADC are designed for input and readout, allowing the proposed CMOS-ReRAM accelerator to achieve up to 15.2× runtime speedup and 498× higher energy efficiency versus the state-of-the-art CMOS-ASIC implementation.