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Article: A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation

TitleA New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation
Authors
KeywordsFinite impulse response model
variable forgetting factor
bias compensation
efficient hardware implementation
Issue Date2020
PublisherIEEE. The Journal's web site is located at https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
Citation
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, v. 67 n. 1, p. 198-211 How to Cite?
AbstractThis paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq ® -7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages.
Persistent Identifierhttp://hdl.handle.net/10722/293358
ISSN
2022 Impact Factor: 5.1
2020 SCImago Journal Rankings: 0.861
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorTAN, H-
dc.contributor.authorChan, SC-
dc.contributor.authorLIN, JQ-
dc.contributor.authorSun, X-
dc.date.accessioned2020-11-23T08:15:35Z-
dc.date.available2020-11-23T08:15:35Z-
dc.date.issued2020-
dc.identifier.citationIEEE Transactions on Circuits and Systems I: Regular Papers, 2020, v. 67 n. 1, p. 198-211-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10722/293358-
dc.description.abstractThis paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq ® -7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919-
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papers-
dc.rightsIEEE Transactions on Circuits and Systems I: Regular Papers. Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectFinite impulse response model-
dc.subjectvariable forgetting factor-
dc.subjectbias compensation-
dc.subjectefficient hardware implementation-
dc.titleA New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation-
dc.typeArticle-
dc.identifier.emailChan, SC: scchan@eee.hku.hk-
dc.identifier.authorityChan, SC=rp00094-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/TCSI.2019.2944221-
dc.identifier.scopuseid_2-s2.0-85078259612-
dc.identifier.hkuros319265-
dc.identifier.volume67-
dc.identifier.issue1-
dc.identifier.spage198-
dc.identifier.epage211-
dc.identifier.isiWOS:000508385000018-
dc.publisher.placeUnited States-
dc.identifier.issnl1549-8328-

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